Logic simulation method
AssigneeFujitsu Limited
InventorsMinoru Shoji, Fumiyasu Hirose
Life of this patent
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Abstract
A logic simulation method and apparatus for sequentially performing a high-speed simulation of a logic circuit designed through sequential processing descriptions. An operation control unit corresponds to each of a plurality of operations described in sequential processing descriptions. The operation control unit controls a start of an operation and determines an end of the operation. After determining an end of a first operation by simulating operation of the operation control unit corresponding to the first operation, a next operation described in sequential processing descriptions is simulated concurrently with simulating an operation control unit corresponding to the next operation until all operations have been sequenced through.
Claims11
A logic simulation method of verifying a logic circuit designed according to sequential processing descriptions, comprising the steps of:
- controlling a start of a first operation described in a sequential processing description with a controlling operation corresponding to said first operation;
- performing the first operation described in said sequential processing descriptions and concurrently simulating said first operation and said controlling operation corresponding to said first operation;
- determining an end of said first operation by simulating said controlling operation corresponding to said first operation;
- and
- after the end of said first operation has been determined by simulating said controlling operation corresponding to said first operation, simulating a next operation described in sequential processing descriptions and concurrently simulating controlling operations corresponding to said next operation.
An event-driven logic simulator for verifying a logic circuit designed corresponding to sequential processing descriptions, comprising:
- first processor means for simulating a gate as a unit delay element, said unit delay being a delay time taken for evaluating an output a logic element forming part of the logic circuit;
- time storing memory means for storing a present time;
- time series input storing memory means for storing in time series an external input received by said first processor means;
- time series output storing memory means for storing external outputs, in time series, of said first processor means;
- and
- second processor means for controlling an entire simulation.
Dependencies are inferred from the claim text.