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US 5,475,831 AGranted
Parallel to serial data transfer system having reduced data processing unit head
AssigneeNEC Corporation
InventorsHiroshi Yoshida, Kenji Nakahara
Life of this patent
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Abstract
A parallel to serial data transfer system includes a CPU for continuously supplying parallel data of plural bytes, a buffer for storing the parallel data transferred from the CPU, a shift resister for loading the parallel data to be converted into serial data, and a selector. The buffer supplies an empty flag to the selector when no data is stored therein, so that the selector supplies a signal to the buffer and the shift resister in order to prohibit a load of parallel data from the buffer to the shift resister.
Claims3
A parallel to serial data transfer system, comprising:
- a data processing unit for supply of parallel data of "m" bytes in a successive manner, where "m" is an integer equal to or larger than 1;
- a buffer for receiving said parallel data of "m" bytes from said data processing unit and holding said parallel data of "m" bytes, said buffer having a capacity of "n" bytes, where "n" is an integer equal to or larger than "m", said buffer also for generating an empty flag when no parallel data is held therein;
- a control circuit for prohibiting a load of parallel data to a shift register, when said empty flag is generated and for generating a read signal as a function of said empty flag;
- and
- a shift register for generating serial data of "m" bytes by being loaded with said parallel data of "m" bytes in a successive manner from said buffer when said read signal is not generated and said empty flag is not generated, and said shift register for generating a constant value a predetermined number of clocks after said empty flag is generated.
2 more elements
Dependencies are inferred from the claim text.