Digital processor having plurality of memories and plurality of arithmetic logic units corresponding in number thereto and method for controlling the same

A method for controlling a digital processor, said digital processor comprising:

• a memory group comprising "m" memories, each memory "i" (i=1 to "m") of said "m" memories having Pi address ports "ij" (j=1 to Pi),
• an arithmetic and logic unit group comprising "n" arithmetic and logic units,
• first arbitration means for receiving and arbitrating outputs of said memory group and for outputting the arbitrated outputs of said memory group to said arithmetic and logic unit group,
• second arbitration means for receiving and arbitrating outputs of said arithmetic and logic unit group and for outputting the arbitrated outputs of said arithmetic and logic unit group to said memory group,
• a plurality of address generation means each for supplying a generated address to said memory group,
• clock supply means for supplying respective clock signals to at least said plurality of address generation means, and
• control circuit for supplying control signals to said memory group, said arithmetic and logic unit, said first arbitration means and said second arbitration means, respectively, in synchronism with the clock signals generated by said clock supply means,
• said control means operating to previously output and respectively set address generation rules to said plurality of address generation means so that the plurality of address generation means, set with the address generation rules, operate to generate an address in accordance with the set address generation rules outputted and respectively set by said control means to said plurality of address generation means and in synchronism with the clock signals supplied from said clock signal supply means, independently of said control means,
• wherein the set address generation rules are maintained effective until they are reset by said control means,
• the method including the steps of:
• selecting at least one of said plurality of address generation means,
• setting an address generation rule to each of the selected address generation means from said control means,
• supplying address generation start signals to said selected address generation means from said control means simultaneously or with a time difference so that each of said selected address generation means starts its address generation and continues to supply an address to a corresponding memory in synchronism with said clock signals and independently of said control means until the address generation indicated by the address generation rules is completed,
• each of said selected address generation means for generating an address generation end signal when an address generation is ended, and a selected one of address generation end signals generated by said selected address generation means being supplied to said control means.