Microprocessor with apparatus for parallel execution of instructions

A microprocessor of a computer system for running a program comprising a sequence of complex instructions selected from a set of complex instructions of variable length, said microprocessor comprising:

• an instruction execution engine;
• first and second instruction pipelines for executing said sequence of complex instructions wherein multiple instructions can be simultaneously executed in parallel;
• instruction decoding means for decoding first and second instructions in said sequence of complex instructions to produce first and second microcode vectors in said first and second instruction pipelines, respectively, and for determining whether said first and second instructions are included within a subset of most frequently executed instructions of said set of complex instructions;
• calculating means for calculating a first length of said first instruction, and a second length of said first and second instructions;
• means for determining whether a register dependency exists between said first and second instructions, said determining means producing a signal in a first state whenever said register dependency exists, said signal being in a second state whenever said register dependency is non-existent;
• and
• means for issuing said first and second microcode vectors and said second length to said execution engine whenever said signal is in said second state and said first and second instructions are included within said subset, said issuing means issuing said first microcode vector and said first length otherwise.

A complex instruction set computer (CISC) for parallel execution of a pair of instructions selected from a complex instruction set, said set including instructions of variable length, said computer comprising:

• an execution engine;
• a first decoder for decoding a first one of said pair of instructions into a first microcode vector;
• second and third decoders, said third decoder for decoding said first one of said pair of instructions, said second decoder for decoding a second one of said pair of instructions into a second microcode vector;
• a circuit coupled to said second and third decoders for generating a first logic signal when a register dependency exists between said pair of instructions, and a second logic signal otherwise;
• means coupled to said first, second, and third decoders for calculating first and second instruction lengths, said first instruction length representing the length of said first one of said pair of instructions, and said second instruction length representing the combined length of said pair of instructions;
• and
• means for coupling said first and second microcode vectors and said second instruction length to said execution engine in response to said second logic signal.