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AssigneeHewlett-Packard Company
InventorsFrederic C. Amerson, Rajiv Gupta, Vinod K. Kathail, Michael S. Schlansker
Estimating the term…
A memory processor which prevents errors when the compiler advances long latency load instructions in the instruction sequence to reduce the loss of efficiency resulting from the latency time. The memory processor intercepts all load and store instructions prior to the instructions entering the memory pipeline. The memory processor stores load instructions for a period of time sufficient to determine if any subsequent store instruction that would have been executed prior to the load instruction, had the load instruction not been moved, references the same address as that specified in the load instruction. If a store instruction references the load instruction address, the invention returns the same data as the load instruction would have if it was not moved by the compiler.
In a data processing system comprising a processor and memory, said memory comprising means for storing data in response to store instructions from said processor and delivering data to said processor in response to lead instructions from said processor, a memory processor for preventing a lead instruction that has been moved in a code sequence from returning erroneous results because of a store instruction to the memory location specified in said lead instruction, said memory processor comprising:
Dependencies are inferred from the claim text.