Reply monitor for a network of microprocessor-based systems

A network of microprocessor-based systems interconnected by a communication channel, wherein at least one of said system comprises:

• decoder means for receiving a reply packet through said communication channel and determining the identity of the microprocessor-based system which transmitted the reply packet and generating a reply interrupt command when a reply packet is received;
• first and second reply monitor circuits associated respectively with first and second microprocessor-based systems, each of the first and second reply monitor circuits being connected to said decoder means for receiving said reply interrupt command therefrom, each of said first and second reply monitor circuits comprising:
• first, second and third flags, said first flag being reset and said third flag being set when a reply packet is received from the corresponding microprocessor-based system via the decoder means;
• a timer arranged to be activated in response to said first flag being set for measuring an amount of time, said timer being deactivated in response to said first flag being reset, said timer setting said second flag when a predetermined amount of time elapses from when said timer is activated if said timer is not deactivated during said predetermined amount of time;
• and
• a microprocessor responsive to transmission of a request packet onto the communication channel for setting said first flag, the microprocessor having a first interrupt port responsive to the setting of said second flag for performing a time-out interrupt routine and a second interrupt port responsive to the setting of said third flag for performing a reply interrupt routine, said microprocessor resetting the second and third flags when the time-out interrupt routine and the reply interrupt routine are respectively performed.