Digital phase-locked loop

Abstract

A digital phase-locked loop includes a digital controller whose output is coupled to a controllable oscillator and which loop comprises a phase detector (PD) whose two inputs are provided to receive a pulse-shaped reference signal (REF) and a pulse-shaped oscillator signal (OSC) generated by the oscillator. This phase detector comprises a first circuit branch provided to receive the reference and the oscillator signal, to form a pulse-shaped signal whose pulse width is equal to the distance in time between two specific successive pulse edges of the reference and oscillator signal, to filter by low-pass filter the pulse-shaped signal and to code sample values of the low-pass filtered signal with a first number (Nf) of least significant bits. This phase detector comprises a second circuit branch, coupled to the first circuit branch, which second branch comprises a counter means which changes its count if no or more than one specific edge of the oscillator signal occur(s) between two successive given edges of the reference signal, which codes the result of the counting with a second number (Ng) of most significant bits.

Dependencies are inferred from the claim text.