Circuit arrangement with at least one input and at least one output for forwarding an input signal that can be filtered, parallelized and digitized
AssigneeSiemens Aktiengesellschaft
InventorsGisbert Lawitzky, Wolf-Dietrich Moller, Franz-Josef Schmitt
Life of this patent
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Abstract
A circuit arrangement (1000, 2000), preferably for a coupling network component of a network node in a packet-switching data network, is disclosed which has a wide parallelization of the data packet signal by means of shift registers (60), so that it is possible to operate internally with a greatly reduced operating speed. In particular, an arrangement of the components on a single semiconductor wafer (3000, 4000) permits an especially wide bus (20), which can be constructed extremely advantageously with a surface-optimized floor plan (3000, 4000).
Claims18
A circuit arrangement with at least one input and at least one output for forwarding an input signal that can be filtered, parallelized and digitized, comprising:
- the at least one input receiving the input signal, and the at least one input connected to an input signal form converter that converts the input signal into an at least partially parallelized bit group packet signal composed of at least one parallel bit group;
- an output filter operatively connected to said input signal form converter for receiving said at least partially parallelized bit group packet signal and forwarding said at least partially parallelized bit group packet signal according to direction information in said at least partially parallelized bit group packet signal received by said output filter, said direction information indicative of a relevant output of said at least one output;
- an intermediate memory connected to said output filter for temporarily storing the at least one parallel bit group of said at least partially parallelized bit group packet signal forwarded by said output filter;
- a forwarding means connected to said intermediate memory for parallel bit group forwarding of the at least one parallel bit group of said intermediately stored bit group packet signal;
- an output signal form converter connected to said forwarding means and to the at least one output, said output signal form converter converting the at least one parallel bit group received from the forwarding means into an output signal on said relevant output of the at least one output.
Dependencies are inferred from the claim text.