Fuzzy multiple signature compaction scheme for built-in self-testing of large scale digital integrated circuits

A method of testing a digital integrated circuit for faults, comprising the steps of:

• (a) establishing a plurality of n check points l.sub.1, l.sub.2, . . . , l.sub.n, where n>1 in a test sequence;
• (b) defining a set of m references, r.sub.1, r.sub.2, . . . , r.sub.m, where m>1, said set of m references corresponding to signatures produced by said digital integrated circuit at said plurality of n check points l.sub.1, l.sub.2, . . . , l.sub.n in the absence of any faults in said digital integrated circuit;
• (c) applying said test sequence to said digital integrated circuit;
• (d) for each check point l.sub.i, where 1.ltoreq.i.ltoreq.n, of said plurality of n check points:
• (i) deriving a signature s.sub.i from said digital integrated circuit at said check point l.sub.i ;
• (ii) comparing said derived signature s.sub.i with members of said set of m references;
• (iii) rejecting said digital integrated circuit if said derived signature does not match any of said members of said set of m references;
• and
• (e) passing said digital integrated circuit if each derived signature s.sub.i matches at least one member of said set of m references.

A method of testing a digital integrated circuit for faults, said method comprising the steps of:

• (a) selecting a sequence of test vectors to apply to said digital integrated circuit;
• (b) breaking said sequence of test vectors into a plurality of n sub-sequences, each of said plurality of n sub-sequences terminating at one of a plurality of n check points l.sub.1, l.sub.2, . . . , l.sub.n ;
• (c) defining a set of m references r.sub.1, r.sub.2, . . . , r.sub.m corresponding to signatures produced by said digital integrated circuit at said plurality of n check points l.sub.1, l.sub.2, . . . , l.sub.n in the absence of any faults in said digital integrated circuit;
• (d) applying said sequence of test vectors to said digital integrated circuit and, at each check point l.sub.i, where 1.ltoreq.i.ltoreq.n, of said plurality of n check points:
• (i) deriving a signature s.sub.i from said digital integrated circuit at said check point l.sub.i ;
• (ii) comparing said derived signature s.sub.i with said set of m references to determine whether or not said derived signature s.sub.i matches any member of said set of m references;
• (iii) passing said digital integrated circuit if, at all of said plurality of n check points, said derived signature s.sub.i matches at least one member of said set of m references;
• and,
• (iv) rejecting said digital integrated circuit if, at any of said plurality of n check points, said derived signature s.sub.i matches no members of said set of m references.