Semiconductor memory device

An integrated circuit device comprising:

• an external terminal;
• a latch circuit receiving first data inputted from outside of said device, said first data having a plurality of bits, said latch circuit latching said first data;
• a memory cell array having a plurality of word lines, a plurality of data lines and a plurality of memory cells, each of said plurality of memory cells being coupled to a corresponding one of said plurality of word lines and at least a corresponding one of said plurality of data lines;
• a circuit writing said first data into predetermined memory cells in said memory cells in accordance with address signals inputted from outside of said device;
• and,
• a circuit receiving first data outputted from said latch circuit and read data read out from said predetermined memory cells, setting said external terminal to a first level when each bit of said first data is coincident with each corresponding bit of said read data, setting said external terminal at a second level when each bit of said first data is coincident with a logical inversion of each corresponding bit of said read data and setting said external terminal to a high-impedance when at least one bit of said first data is coincident with a corresponding bit of said read data and at least another one bit of said first data is coincident with a logical inversion of a corresponding bit of said read data at the same time.