US 5,475,649 A · Dual-port memory has the serial register connected to the storage cells by single-sided bitlines

Abstract

A dual-port memory includes an array of dynamic storage cells and a serial register having a plurality of static stages. Each stage of the serial register is arranged for receiving a data bit from a selected storage cell of the array. A plurality of bitlines is interposed between the storage cells of the array and the stages of the serial register. At one time only a single selectable bitline is arranged for interconnecting each of the columns of storage cells with each of the stages of the serial register. Each stage of the serial register includes a latch disabling circuit for selectively enabling and disabling coupling from an output of one amplifier to an input of another amplifier. By disabling such coupling, new data easily can be written into the serial register stage. A keeper circuit in each stage of the serial register reduces power consumption.

Claims5

Dependent claims

A dual-port memory comprising:

an array of storage cells arranged in addressable rows and columns;
a serial register having a plurality of stages, each stage being arranged for receiving a data bit from a selected storage cell;
a plurality of bitline leads, only a single bitline lead interconnecting a column of storage cells to each different stage of the serial register;
and
the plurality of stages are static circuits, each including a latch disabling circuit for facilitating write in of new data.

2 more elements

Dependencies are inferred from the claim text.

Dual-port memory has the serial register connected to the storage cells by single-sided bitlines

Life of this patent

Dual-port memory has the serial register connected to the storage cells by single-sided bitlines

Life of this patent

Abstract

Claims5