US 5,475,648 A · Redundancy semiconductor memory device which utilizes spare memory cells from a plurality of different memory blocks, and utilizes the same decode lines for both the primary and spare memory cells

Abstract

A semiconductor memory device with a redundancy configuration with a higher corrective efficiency is disclosed. Primary memory cell arrays 3a, 3b, and 3c are arranged in memory cell blocks a, b, and c. spare memory cell arrays 2b and 2c are arranged in the memory cell blocks b and c. When the address of an address signal supplied agrees with the address of a defective primary memory cell in one memory cell block, a spare memory cell in the other memory cell block selected for such a defective memory cell. Even if a word line of the primary and a word line of the spare memory cells are selected at the same time, it is possible to access read data in a nondestructive manner. This achieves a high-speed word line activation as well as an improved corrective efficiency. The provision of a row decoder that connects a primary word line to a spare word line with a shared decode line prevents the increase of the area of memory chips due to the arrangement of a Spare memory cell.

Claims9

Dependent claims

A semiconductor memory device with a plurality of primary memory cells and a plurality of spare memory cells, the semiconductor memory device comprising:

decoder means for interconnecting the primary memory cell and the spare memory cell through a shared decode line which is driven through a shared word line drive signal generating circuit;
and
memory replacement means coupled to said decoder means for storing in advance an address of a defective memory cell of the plurality of primary memory cells and makes, when an address signal corresponding to a memory cell to be accessed agrees with the address of the defective memory cell, the decoder means operates to select the spare memory cell to replace the defective primary memory cell.

A semiconductor memory device comprising:

a plurality of memory cell blocks each containing a plurality of memory cells, wherein a fraction of the memory cells of at least one of said memory cell blocks function as primary memory cells and the remaining memory cells function as spare memory cells,
decoder means for accessing word lines of said primary and said spare memory cells of said at least one of said memory cell blocks, said decoder means comprising a plurality of decode lines for supplying a drive signal to said word lines of said primary and said spare memory cells, said word lines of said primary memory cells and spare memory cells are connected by a plurality of shared decode lines and are driven through a shared word line drive signal generation circuit, and
memory replacement means for controlling said decoder means such that when a requested memory cell address corresponds to a defective primary memory cell the decoder means operates to select a spare memory cell selected to replace said defective primary memory cell, wherein said spare memory cell is defined to be selectable from a memory cell block other than the memory cell block containing said defective primary memory cell.

Dependencies are inferred from the claim text.

Redundancy semiconductor memory device which utilizes spare memory cells from a plurality of different memory blocks, and utilizes the same decode lines for both the primary and spare memory cells

Life of this patent

Redundancy semiconductor memory device which utilizes spare memory cells from a plurality of different memory blocks, and utilizes the same decode lines for both the primary and spare memory cells

Life of this patent

Abstract

Claims9