US 5,475,647 AGranted

Flash write circuit for a semiconductor memory device

AssigneeSamsung Electronics Co., Ltd.

InventorsSung-Min Yim, Jang-Kyu Lee, Min-Tea Kim, Seong-Ook Jung

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Abstract

A semiconductor memory device having a plurality of memory blocks and a plurality of I/O control circuits operatively associated with respective ones of the memory blocks. Each of the I/O control circuits includes a flash write enable signal generator responsive to a flash write mode indication signal and a respective memory block address signal, for generating a memory block specific flash write enable signal. Each of the I/O control circuits further includes a plurality of first column selectors connected between respective first alternate pairs of bit lines and respective first data input/output lines, a plurality of second column selectors connected between respective second alternate pairs of bit lines and respective second data input/output lines, and a plurality of flash write control logic circuits responsive to the memory block specific flash write enable signal and a respective one of a plurality of column select signals for generating a corresponding plurality of column selector drive signals. The first column selectors are responsive to respective ones of the column selector drive signals for selectively coupling data to/from respective ones of the first alternate pairs of the bit lines from/to the first data input/output lines. The second column selectors are responsive to respective ones of the column selector drive signals for selectively coupling data to/from respective ones of the second alternate pairs of the bit lines from/to the second data input/output lines.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a plurality of memory blocks, each of which includes a matrix of intersecting bit lines and word lines, and a multiplicity of memory cells coupled to respective ones of said bit lines and said word lines adjacent the intersections thereof;
wherein said bit lines are shared in common by said memory blocks;
wherein said bit lines are identified by respective column select signals;
wherein said memory blocks are identified by respective memory block address signals;
a plurality of I/O control circuits operatively associated with respective ones of said memory blocks, each of said I/O control circuits including:
a flash write enable signal generator responsive to a flash write mode indication signal and a respective one of said memory block address signals for generating a memory block specific flash write enable signal;
a pair of first data input/output lines;
a pair of second data input/output lines;
a plurality of first column selectors connected between respective first alternate pairs of said bit lines and said first data input/output lines;
a plurality of second column selectors connected between respective second alternate pairs of said bit lines and said second data input/output lines;
a plurality of flash write control logic circuits each of which is responsive to said memory block specific flash write enable signal and a respective one of said column select signals for generating a corresponding plurality of column selector drive signals;
wherein said first column selectors are responsive to respective ones of said column selector drive signals for selectively coupling data to/from respective ones of said first alternate pairs of said bit lines from/to said first data input/output lines;
and,
wherein said second column selectors are responsive to respective ones of said column selector drive signals for selectively coupling data to/from respective ones of said second alternate pairs of said bit lines from/to said second data input/output lines.

11 more elements

A semiconductor memory device, comprising:

a plurality of memory blocks, each of which includes a matrix of intersecting bit lines and word lines, and a multiplicity of memory cells coupled to respective ones of said bit lines and said word lines adjacent the intersections thereof;
wherein said bit lines are shared in common by said memory blocks;
wherein said bit lines are identified by respective column select signals;
wherein said memory blocks are identified by respective memory block address signals;
a plurality of I/O control circuits operatively associated with respective ones of said memory blocks, each of said I/O control circuits including:
a flash write signal generator responsive to a flash write mode indication signal and a respective one of said memory block address signals for generating a memory block specific flash write enable signal;
a pair of first data input/output lines;
a pair of second data input/output lines;
a plurality of first column selectors connected between respective first alternate pairs of said bit lines and said first data input/output lines, said first column selectors being responsive to respective ones of said column select signals for selectively coupling data to/from respective ones of said first alternate pairs of said bit lines from/to said first data input/output lines;
a plurality of second column selectors connected between respective second alternate pairs of said bit lines and said second data input/output lines, said second column selectors being responsive to respective ones of said column select signals for selectively coupling data to/from respective ones of said second alternate pairs of said bit lines from/to said second data input/output lines;
a plurality of third column selectors connected between respective first alternate pairs of said bit lines and said first data input/output lines in parallel with said first column selectors, said third column selectors being responsive to a respective one of said memory block specific flash write enable signals for selectively coupling data to/from respective ones of said first alternate pairs of said bit lines from/to said first data input/output lines;
and,
a plurality of fourth column selectors connected between respective second alternate pairs of said bit lines and said second data input/output lines in parallel with said second column selectors, said fourth column selectors being responsive to said respective one of said memory block specific flash write enable signals for selectively coupling data to/from respective ones of said second alternate pairs of said bit lines from/to said second data input/output lines.

10 more elements

A semiconductor memory device having a plurality of memory blocks, comprising:

a plurality of flash write enable signal generators operatively associated with respective ones of said memory blocks, each of said flash write enable signal generators including a logic AND gate having a first input coupled to a flash write enable signal and a second input coupled to a respective memory block selection signal, the output of said logic AND gate of each said flash write enable signal generator constituting a respective memory block specific flash write enable signal;
and,
a plurality of column selector drive signal generators operatively associated with each of said memory blocks, each of said column selector drive signal generators including a logic OR gate having a first input coupled to a respective column select signal and a second input coupled to a respective memory block specific flash write enable signal, the output of each of said column selector drive signal generators constituting a control signal which is coupled to a respective one of a plurality of column selectors each of which is connected between a respective bit line and a respective data input/output line of the semiconductor memory device.

Dependencies are inferred from the claim text.