Crosspoint memory

A memory having interconnection pins and comprising:

• an array of dual-port switching memories implemented as first-in, first-out memory devices;
• each of said dual-port switching memories comprising a plurality of memory cells arranged in a matrix of rows and columns and respectively defined by memory elements, the memory elements of each of said memory cells providing a respective bit of the dual-port switching memory in which the memory cell is located;
• each of said dual-port switching memories included in the array of dual-port switching memories including a write-only port and a read-only port having separate address and control signals;
• the write-only port of each of said dual-port switching memories having an input buffer;
• a data input bus to which said input buffer of each of said dual-port switching memories is connected bit by bit;
• separate write lines for each bit of a respective dual-port switching memory connected between the input buffer and the memory elements providing the bit of the dual-port switching memory;
• a column selection circuit connected to the input buffers of each row of dual-port switching memories by write enable lines for delivering to the input buffers corresponding write enable signals which are separate for each input buffer of each row;
• a decoder and write address command circuit common to each row of dual-port switching memories for decoding the row addresses and for selecting the corresponding word line in all of the dual-port switching memories of a row of the array of dual-port switching memories;
• and
• externally controlled switches interconnecting the write lines of the dual-port switching memories of one column of the array of dual-port switching memories for modifying, upon request, the storage capacity of a dual-port switching memory, thereby modifying the first-in, first-out memory device implemented thereby.