Semiconductor signal line system with crosstalk reduction

A signal line system for a plurality of signal lines comprising:

• a first pair of signal lines for connecting a pair of devices, the pair of devices being separated from one another along a predetermined direction;
• a second pair of signal lines, at least one portion of a first line of said signal lines of said second pair being disposed between said signal lines of said first pair, said signal lines of said second pair crossing each other at at least a first crossing point and a second crossing point;
• a third pair of signal lines, at least one portion of a first line of said signal lines of said third pair being disposed between one of said signal lines of said first pair and said first signal line of said second pair, said signal lines of said third pair crossing each other at at least a third crossing point and
• wherein an adjacent first signal line adjacent to said second pair at said first crossing point is straight and parallel to said predetermined direction at a corresponding first point along said adjacent line, said corresponding first point along said adjacent first signal line being aligned with said first crossing point in a direction substantially perpendicular to said predetermined direction,
• wherein an adjacent second signal line adjacent to said second pair at said second crossing point is straight and parallel to said predetermined direction at a corresponding second point along said adjacent second signal, line, said corresponding second point along said adjacent second signal signal line being aligned with said second crossing point in a direction substantially perpendicular to said predetermined direction,
• wherein an adjacent third signal line adjacent to said third pair at said third crossing point is straight and parallel to said predetermined direction at a corresponding third point along said adjacent third signal line, said corresponding third point along said adjacent third signal signal line being aligned with said third crossing point in a direction substantially perpendicular to said predetermined direction,
• wherein said third crossing point is offset along said predetermined direction relative to said first and second crossing points, and
• wherein said each of said pairs of signal lines include bit lines connected between memory cells and sense amplifiers. respectively.