Dynamic random access memory with bit line preamp/driver

A random access memory, comprising:

• a plurality of single transistor memory cells configured in an array and each having a memory capacitor for storing a logic "0" voltage or a logic "1" voltage;
• an inner Bit Line;
• an access device for selectively connecting one of said memory cells to said inner Bit Line in response to an external access signal such that said memory capacitor can transfer charge to and from said inner Bit Line;
• an outer Bit Line;
• a Bit Line preamp/driver circuit for driving said outer Bit Line from a source different from said inner Bit Line as said access device accesses said memory cell, such that said outer Bit Line is not directly coupled to said inner Bit Line, said outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in said accessed memory cell;
• and
• a precharge device for precharging said inner Bit Line to a predetermined voltage, said Bit Line preamp/driver circuit operable to shift the voltage on said outer Bit Line to a voltage higher than that on said inner Bit Line for at least one logic state stored in said memory cell.

A method for accessing data stored in one of a plurality of single transistor memory cells, each memory cell having a memory capacitor for storing a logic "0" or a logic "1" voltage, comprising the steps of:

• providing an inner Bit Line;
• accessing one of the single transistor memory cells and connecting the associated memory capacitor to the inner Bit Line such that the memory capacitor can transfer charge to and from the inner Bit Line;
• providing an outer Bit Line;
• driving the outer Bit Line from a source different than the inner Bit Line as the memory cell is accessed during the step of accessing the memory cell, such that the outer Bit Line is not directly coupled to the inner Bit Line, the outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in the accessed memory cell;
• and
• sensing the logic state on the outer Bit Line during a step of restoring, and driving the voltage on the outer Bit Line to a full logic voltage or to a ground voltage, respectively, during a Restore operation, and substantially concurrently driving the inner Bit Line to the same voltage that is on the outer Bit Line.

A method for accessing data stored in one of a plurality of single transistor memory cells, each memory cell having a memory capacitor for storing a logic "0" or a logic "1" voltage, comprising the steps of:

• providing an inner Bit Line;
• accessing one of the single transistor memory cells and connecting the associated memory capacitor to the inner Bit Line such that the memory capacitor can transfer charge to and from the inner Bit Line;
• providing an outer Bit Line;
• driving the outer Bit Line from a source different than the inner Bit Line as the memory cell is accessed during the step of accessing the memory cell, such that the outer Bit Line is not directly coupled to the inner Bit Line, the outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in the accessed memory cell;
• and
• precharging the inner Bit Line to a predetermined voltage, wherein the step of driving the outer Bit Line from a source different from the inner Bit Line comprises shifting the voltage on the outer Bit Line to a voltage higher than that on the inner Bit Line for at least one logic state on the memory cell.