US 5,475,639 AGranted

Semiconductor memory device with improved speed for reading data

AssigneesFujitsu Limited, Fujitsu VLSI Limited

InventorsAkihiro Iwase, Teruo Seki, Shinji Nagai, Tadashi Ozawa

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Abstract

Disclosed is a semiconductor memory device which operates based on voltages from a high voltage power source and a low voltage power source. A plurality of memory cells are formed in a memory cell array. Plural pairs of bit lines are connected to the memory cells to transfer data signals read from the memory cells. A sense amplifier, which has a pair of input terminals, amplifies the data signal. A level shifter is selectively connected to plural pairs of bit lines to shift the level of the data signal of a selected pair of bit lines to a level near the operation point of the sense amplifier, and supplies a resultant data signal to the sense amplifier. The level shifter includes a first transistor for receiving the data signal, and a plurality of second transistors connected between the first transistor and the low voltage power source. The first transistor has a first terminal to be supplied with the data signal, a second terminal and a control electrode for receiving a control signal for transferring the data signal to the sense amplifier. The second transistors are connected between the second terminal of the first transistor and the low voltage power source. The output of the second terminal of the first transistor is input to the input terminals of the sense amplifier.

Claims9

Dependent claims

A semiconductor memory device operable based on voltages from a high voltage power source and a low voltage power source comprising:

a plurality of memory cells formed in a memory cell array;
a plurality of pairs of bit lines, connected to said memory cells, for communicating data signals read from said memory cells;
a sense amplifier, coupled to said plurality of pairs of bit lines, having a pair of input terminals for receiving a data signal and for amplifying said data signal;
and
a level shifter to which said plurality of pairs of bit lines are selectively connected, said level shifter operating to shift a level of said data signal of a selected pair of bit lines to a level in a vicinity of an operation point of said sense amplifier and which supplies a resultant data signal to said sense amplifier,
said level shifter comprising,
a first transistor for receiving said data signal and having a first terminal to be supplied with said data signal, a second terminal, and a control electrode for receiving a control signal in order to transfer said data signal to the input terminals of said sense amplifier and said second terminal, and
a plurality of second transistors connected between said second terminal of said first transistor and said low voltage power source, wherein said second terminal of the first transistor outputs the signal to the sense amplifier.

5 more elements

Dependencies are inferred from the claim text.