US 5,475,638 AGranted

Static random access memory device having a single bit line configuration

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsKenji Anami, Toshihiko Hirose, Shuji Murakami, Kojiro Yuzuriha, Tadato Yamagata

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Abstract

A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Claims21

Dependent claims

A static random access memory device comprising:

a memory cell array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns,
a plurality of bit lines, each being provided in a corresponding column in said memory cell array and connected to a memory cell of said corresponding column,
wherein each of said memory cells comprises
data storage means having a single input/output node for storing a data signal provided via said input/output node,
switching means connected between a bit line in a corresponding column and said input/output node, said switching means attaining a conductive state in response to row and column address signals, and
status control means responsive to an externally applied write control signal for stabilizing and unstabilizing the data storage state of the data storage means in a memory cell selected by row and column address signals.

3 more elements

Dependencies are inferred from the claim text.