Asynchronous digital sample rate converter
AssigneeAnalog Devices, Inc.
InventorsRobert W. Adams, Tom W. Kwan, Michael Coln
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AssigneeAnalog Devices, Inc.
InventorsRobert W. Adams, Tom W. Kwan, Michael Coln
Estimating the term…
An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.
A system for converting a sequence of input samples at a first sampling rate to a sequence of output samples at a second sampling rate, the system comprising:
A system for converting a sequence of input samples at a first sampling rate defining an input period to a sequence of output samples at a second sampling rate, comprising:
A system for convening a first sequence of input samples at a first sampling rate to a second sequence of output samples m a second sampling rate, comprising:
A digital integrated circuit for convening a sequence of input samples arriving at a first sampling rate defining an input period to a sequence of output samples at a second sampling rate and having an input for receiving a master clock signal from an external signal source, the master clock signal having a frequency independent of and substantially higher than the first and second sampling rates, and comprising:
A method for converting a sequence of input samples at a first sampling rate to a sequence of output samples at a second sampling rate, comprising the steps of:
A method for converting a sequence of input samples at a first sampling rate defining an input period to a sequence of output samples at a second sampling rate, using a set of filter coefficients stored in a memory comprising the steps of:
A method for converting a first sequence of input samples at a first sampling rate to a second sequence of output samples at a second sampling rate using a set of filter coefficients stored in a memory, given a first coefficient address related to the first and second sampling rates comprising the steps of:
A method for convening a sequence of input samples arriving at a first sampling rate defining in input period to a sequence of output samples at a second sampling rate, using a set of filter coefficients stored in a memory, comprising the steps of:
Dependencies are inferred from the claim text.