US 5,475,624 A · Test generation by environment emulation

Abstract

Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit. A fault dictionary is produced which includes an indication of the test vector at which each fault is detected, the output signal differences indicative of fault detection, and a log of the faults detected. The faultable emulation is also used for device testing by comparing its outputs to those of a logic circuit, and injecting selected faults (for example, those indicated by comparing failure patterns to fault dictionary entries) to aid in device debug. Techniques are described for modeling faults, sequentially activating the faults in hardware time, preparing a fault dictionary, and extracting a test program in a format adaptable to standard ATE systems, and testing a debugging devices by comparing their behavior to that of a faultable emulation model of the device.

Claims28

Dependent claims

A method for generating a record of faults detected by a pattern of test vectors applied to a logic device, comprising the steps of:

a. creating a first emulation of a logic device;
b. creating a second emulation of the logic device;
c. selectively introducing a fault into the second emulation;
d. applying a pattern of test vectors to the first emulation and to the second emulation, to thereby exercise the first emulation and the second emulation;
e. comparing output signals produced by the first emulation and the second emulation in response to each test vector of the pattern, to thereby detect the selectively introduced fault by detecting any difference between the output signals;
f. upon detection of the selectively introduced fault, producing a record identifying the fault introduced into the second emulation;
and
g. repeating steps c.-f. for each of a sequence of selectively introduced faults, to thereby produce a record identifying which faults of the sequence of faults result in differences between the output signals of the first emulation and the second emulation.

5 more elements

A method of concurrently developing an integrated circuit design and a pattern of test vectors suitable for production testing of integrated circuits constructed in accordance with the design, comprising the steps of:

a. preparing a design of an integrated circuit;
b. preparing a set of test vectors for exercising the integrated circuit;
c. creating a non-faulted emulation of the integrated circuit;
d. creating a faultable emulation of the integrated circuit;
e. selectively introducing one of a sequence of faults in the faultable emulation;
f. applying a pattern of test vectors to the non-faulted emulation and to the faultable emulation, to thereby exercise the non-faulted emulation and the faultable emulation;
g. comparing output signals produced by the non-faulted emulation and the faultable emulation in response to each test vector of the applied pattern of test vectors, to thereby detect the selectively introduced fault by detecting any difference between the output signals;
h. repeating steps e.-g. for each fault of the sequence of faults;
i. determining an extent of fault coverage by comparing the number of detected faults with a count of the number of faults introduced in the faultable emulation:
j. modifying the design of the integrated circuit and the pattern of test vectors;
and
k. repeating steps b.-i., for each modification of the design of the integrated circuit and the pattern of test vectors.

9 more elements

A method of testing a device having a logic circuit and input pins and output pins, comprising the steps of:

a. preparing a fault dictionary comprising an entry for each of a plurality of possible faults in the device, each said entry identifying the fault and a test vector of a test vector pattern at which said fault is exhibited at output pins of the device when the test vector pattern is applied to input pins of the device;
b. preparing an emulation model of the device by programming a plurality of gates of a programmable gate array, said emulation model having input lines and output lines corresponding to input pins and output pins of the device;
c. applying the test vector pattern to input pins of the device and to input lines of the emulation model, to thereby exercise the device and the emulation model;
d. for each test vector of the applied test vector pattern, comparing signals appearing at output pins of the device with signals appearing at output lines of the emulation model to produce a comparison signal indicative of any difference between the signals appearing at output pins of the device and the signals appearing at output lines of the emulation model;
e. upon detection of any said difference, recording said comparison signal and an identification of a test vector at which said difference is detected;
and
f. comparing the identification of a test vector recorded in step e. with entries of said fault dictionary to identify at least one possible fault in the device which can produce said difference.

4 more elements

A method of testing a device having a logic circuit and input pins and output pins, comprising the steps of:

a. preparing a fault dictionary comprising an entry for each of a plurality of possible faults in the device, each said entry identifying the nature of the fault and a test vector of a test vector pattern at which said fault is exhibited at output pins of the device when the test vector pattern is applied to input pins of the device, and a failure pattern representation of signals at output pins of the device when said fault is exhibited, wherein multiple entries have identical failure pattern representations;
b. preparing an emulation model of the device by programming a plurality of gates of a programmable gate array, said emulation model having input lines and output lines corresponding to input pins and output pins of the device;
c. applying the test vector pattern to input pins of the device and to input lines of the emulation model, to thereby exercise the device and the emulation model;
d. for each test vector of the applied test vector pattern, comparing signals appearing at output pins of the device with signals appearing at output lines of the emulation model to produce a comparison signal indicative of any difference between the signals appearing at output pins of the device and the signals appearing at output lines of the emulation model;
e. upon detection of any said difference, recording said comparison signal and an identification of a test vector at which said difference is detected;
f. comparing the identification of a test vector recorded in step e. with entries of said fault dictionary to determine the nature of at least one possible fault in the device which cap produce said difference and to determine whether the fault dictionary entry for said at least one possible fault has a unique failure pattern representation;
and
g. preparing a revised test vector pattern capable of exercising the device and the emulation model in a manner which will distinguish between said at least one possible fault and other possible faults for which the fault dictionary entries include identical failure patterns.

5 more elements

Dependencies are inferred from the claim text.

Test generation by environment emulation

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Test generation by environment emulation

Life of this patent

Abstract

Claims28