Method of target generation for multilevel hierarchical circuit designs

A method of generating delay targets for creating a multilevel hierarchical circuit design, comprising the steps of:

• (a) providing a hierarchical design description and delay constraints of the multilevel hierarchical circuit design, wherein the hierarchical design description describes the interrelationship between cells, including macro cells, input/output ports, and nets in the mutilevel hierarchical design;
• (b) generating a net measure for each net and macro cell of the multilevel hierarchical circuit design and generating an abstract delay model for each macro cell of the multilevel hierarchical circuit design based on the hierarchical design description, wherein net measure is the estimated resistive-capacitive delay of a net derived from the estimated length of the net based on area-driven design, and an abstract delay model is a description of delays through a macro cell;
• (c) generating delay targets for the nets and macro cells based on net measures, the abstract delay models and the delay constraints;
• and
• (d) creating the multilevel hierarchical circuit design based on said delay targets.