Image processing apparatus for binarizing multi-value image data
AssigneeCanon Kabushiki Kaisha
InventorShuichi Kumada
Life of this patent
Estimating the term…
Abstract
An image processing apparatus having a process of binarizing a multi-value image data includes a unit for inputting a multi-value image data and first pattern information for a binarization process; a first memory for storing the first pattern information; and a binarizing unit for binarizing the inputted multi-value image data using the first pattern information stored in the first memory. The apparatus further includes a second memory for storing in advance second pattern information, wherein the apparatus has a first mode during which the inputted multi-value image data is binarized using the first pattern information, and a second mode during which the inputted multi-value image data is binarized using the second pattern information.
Claims21
An image processing apparatus for converting multi-value pixel data representing a gradation, outputted from a host computer, into binarized pixel data, said apparatus comprising:
- means for inputting from the host computer first pattern information for a binarization process;
- first storage means for storing said first pattern information inputted by said inputting means;
- and
- binarizing means for binarizing inputted multi-value pixel data using said first pattern information stored in said first storage means, and for generating the binarized pixel data.
An image processing apparatus for outputting binarized pixel data converted from multi-value pixel data supplied from an external apparatus, said apparatus comprising:
- input means for inputting from said external apparatus multi-value pixel data representing a first gradation value and first binarization patterns, said first binarization patterns corresponding to a second gradation value;
- a register for registering the first binarization patterns inputted by the input means;
- and
- a ROM, for storing in advance, a second binarization pattern corresponding to each of the first gradation value and the second gradation value,
- wherein, after the first binarization patterns are registered in said register, said apparatus is operable in a first mode during which said apparatus outputs the binarized pixel data by using said first binarization patterns and a second mode during which said apparatus outputs the binarized pixel data by using said second binarization pattern.
Dependencies are inferred from the claim text.