Double scan circuit for inserting a new scan line between adjacent scan lines of a television

A double scan circuit comprising:

• first data generating means for generating n-bit real line data;
• second data generating means for generating n-bit interpolated line data by line-interpolating an interlace scan signal;
• control means for generating a control signal for discriminating between the real line data and the interpolated line data every horizontal line period, a write clock signal having a predetermined frequency, and a read clock signal whose frequency is 2m times the frequency of the write clock signal, wherein m is an integer greater than one;
• first data converting means for converting the n-bit real line data into 2n-bit real data;
• second data converting means for converting the n-bit interpolated line data into 2n-bit interpolated line data;
• first memory means in which the converted real line data is stored, for reading out the stored data in accordance with the read clock signal;
• second memory means in which the converted interpolated line data is stored, for reading out the stored data in accordance with the write clock signal;
• memory controlling means for generating a write/read control signal of said first and second memory means, a write address and a read address at 2m times the speed of that for the write address, in accordance with the real/interpolated line control signal and the write clock signal, for applying them to said first and second memory means, and for generating a mixing control signal for mixing the real line data with the interpolated line data stored in said first and second memory means for double scanning;
• and
• double scan data generating means for selecting one between the 2n-bit real line data and the 2n-bit interpolated line data in accordance with the mixing control signal and real/interpolated line control signal and for producing the selected one as n-bit double scan data.