Multiple interconnected ring oscillator circuit

An array oscillator circuit, comprising:

• a first ring oscillator having a plurality of first buffer stages defining a plurality of first oscillator output ports;
• a second ring oscillator having a plurality of second buffer stages defining a plurality of second oscillator output ports, each of said plurality of second buffer stages being coupled to a respective one of said plurality of first oscillator output ports, wherein each of said plurality of first buffer stages includes a buffer output port for defining one of said plurality of first oscillator output ports, each of said plurality of second buffer stages including an input coupling port connected to a respective one of said plurality of first oscillator output ports;
• and
• a multiplexer for providing an electrical connection to a selected one of said pluralities of first and second oscillator output ports.

An array oscillator circuit, comprising:

• a first ring oscillator having a plurality of first buffer stages defining a plurality of first oscillator output ports, wherein each of said plurality of first buffer stages includes a signal input port, an input coupling port and a buffer output port, each of said buffer output ports of said plurality of first buffer stages being connected to the signal input port of another of said plurality of first buffer stages;
• a second ring oscillator having a plurality of second buffer stages defining a plurality of second oscillator output ports, each of said plurality of second buffer stages being coupled to a respective one of said plurality of first oscillator output ports;
• and
• a multiplexer for providing an electrical connection to a selected one of said pluralities of first and second oscillator output ports.

An array oscillator circuit, comprising:

• a first ring oscillator having a plurality of first buffer stages defining a plurality of first oscillator output ports, wherein each of said plurality of first buffer stages includes a signal input port, an input coupling port and a buffer output port, each of said buffer output ports of said plurality of first buffer stages being connected to the signal input port of another of said plurality of first buffer stages;
• a second ring oscillator having a plurality of second buffer stages defining a plurality of second oscillator output ports, each of said plurality of second buffer stages being coupled to a respective one of said plurality of first oscillator output ports wherein each of said plurality of second buffer stages includes a signal input port, an input coupling port and a buffer output port, each of said buffer output ports of said plurality of second buffer stages being connected to the signal input port of another of said plurality of second buffer stages and each of said input coupling ports of said plurality of second buffer stages being connected to the buffer output port of one of said plurality of first buffer stages,
• wherein each of said input coupling ports of said plurality of first buffer stages is connected to the buffer output port of one of said plurality of second buffer stages;
• and
• a multiplexer for providing an electrical connection to a selected one of said pluralities of first and second oscillator output ports.

In a phase locked loop having a phase comparator for determining phase difference between a reference signal and an oscillator output signal, said phase locked loop further including an integrator connected between said phase comparator and a loop filter, an array oscillator circuit comprising:

• a first ring oscillator having a plurality of first buffer stages defining a plurality of first oscillator output ports, each of said plurality of first buffer stages including a bias port connected to said loop filter;
• a second ring oscillator having a plurality of second buffer stages defining a plurality of second oscillator output ports at least one of which is disposed to provide said oscillator output signal to said phase comparator, each of said plurality of second buffer stages having an input coupling port coupled to one of said first oscillator output ports and a bias port connected to said loop filter;
• and
• a multiplexer for providing an electrical connection to a selected one of said pluralities of first and second oscillator output ports.

An time digitizer circuit, comprising:

• an array oscillator including:
• a first ring oscillator having a plurality of first buffer stages defining a plurality of first oscillator output ports,
• a second ring oscillator having a plurality of second buffer stages defining a plurality of second oscillator output ports, each of said plurality of second buffer stages being coupled to a respective one of said plurality of first oscillator output ports;
• a plurality of bit lines, each of said bit lines being selectively connected to one of said first plurality of oscillator output ports and to one of said second plurality of oscillator output ports;
• a plurality of latches, each of said latches being connected to one of said bit lines and being driven by an input signal;
• and
• a converter circuit, connected to said plurality of latches, for producing a digitized time representation of said input signal.

A coupled ring oscillator comprising:

• a first ring oscillator having a first plurality of buffer stages wherein first and second inputs of said first ring oscillator are connected to an input one of said first plurality of buffer stages, said first ring oscillator having a first output connected to said second input;
• and
• a second ring oscillator having a second plurality of buffer stages wherein third and fourth inputs of said second ring oscillator are connected to a first one of said second plurality of buffer stages wherein said third input is connected to said first output of said first ring oscillator, said second ring oscillator having a second output connected to said fourth input;
• wherein said first ring oscillator includes a dual-input inverting buffer and a sequence of single-input inverting buffers serially connected to an output of said dual-input inverting buffer.

A phase bisector comprising:

• a phase-frequency comparator having a first input for receiving a reference clock signal;
• a charge pump responsive to control signals provided by said phase-frequency comparator;
• a first ring oscillator having an output connected to a second input of said phase-frequency comparator;
• a second ring oscillator having first and second inputs to which are applied first and second input signals of an input frequency and of first and second phases, respectively, said second ring oscillator producing an output signal having a phase approximately equivalent to an average of said first and second phases;
• and
• a low-pass filter, coupled to said charge pump, for producing a control voltage used to set the oscillation frequencies of said first and second ring oscillators to said input frequency.

An array oscillator circuit, comprising:

• a first ring oscillator having a plurality of first buffer stages defining a plurality of first oscillator output ports, wherein each of said first buffer stages includes:
• a differential transistor pair having first and second drain outputs and a common source output, and
• a transistor current source coupled to the common source output;
• a second ring oscillator having a plurality of second buffer stages defining a plurality of second oscillator output ports, each of said plurality of second buffer stages being coupled to a respective one of said plurality of first oscillator output ports;
• and
• a multiplexer for providing an electrical connection to a selected one of said pluralities of first and second oscillator output ports.

An array oscillator circuit, comprising:

• a first ring oscillator having a plurality of first buffer stages defining a plurality of first oscillator output ports;
• a second ring oscillator having a plurality of second buffer stages defining a plurality of second oscillator output ports, each of said plurality of second buffer stages being coupled to a respective one of said plurality of first oscillator output ports, wherein each of said first and second buffer stages includes a current source bias circuit, said current source bias circuit comprising:
• a half-buffer replica of anyone of said first or second buffer stages, and
• an amplifier coupled to said half-buffer replica;
• and
• a multiplexer for providing an electrical connection to a selected one of said pluralities of first and second oscillator output ports.