An operational amplifier circuit comprising:
- first and second p-channel input transistors (38, 39) having commonly connected sources and having their gates respectively connected to receive first and second input signals;
- a first current source (40) connected between the commonly connected sources of the first and second input transistors and a positive power supply;
- a first n-channel transistor (41) having its drain connected to the drain of the first input transistor and its source connected to a negative power supply;
- a second n-channel transistor (42) having its drain connected to the drain of the second input transistor and its source connected to the negative power supply;
- first and second n-channel current mirror transistors (34, 35) having commonly connected gates coupled to the positive power supply via a second current source (44), the source of the first current mirror transistor (34) being coupled to the drain-drain connection between the first input transistor (38) and the first n-channel transistor (41), the source of the second current mirror transistor (35) being coupled to the drain-drain connection between the second input transistor (39) and the second n-channel transistor (42);
- a third n-channel transistor (43) having its gate commonly connected to the gates of the first and second n-channel transistors (41, 42), its source connected to the negative power supply and its drain connected to the commonly-connected gates of the first and second n-channel current mirror transistors (34, 35) via a resistive element (45), the commonly-connected gates of the first, second and third n-channel transistors (41, 42, 43) being connected to the connection between the resistive element (45) and the drain of the third n-channel transistor (43);
- first, second and third series-connected p-channel transistors (18, 14, 17) connected between the positive power supply and a third current source (33), the third current source being further connected to the negative power supply;
- first and second p-channel current mirror transistors (19, 20) having their gates commonly connected to the gate of the first series-connected transistor (18) and to the drain-source connection between the second and third series-connected transistors (14, 17), the source of the first p-channel current mirror transistor (19) and the source of the second current mirror transistor (20) being connected to the positive power supply, the drain of the first p-channel current mirror transistor (19) being connected to the drain of the first n-channel current mirror transistor (34), the drain of the second p-channel current mirror transistor (20) being connected to the drain of the second n-channel current mirror transistor (35);
- third and fourth p-channel current mirror transistors (15, 21) having their commonly connected gates connected to the commonly connected gates of the second and third series-connected transistors (14, 17), the gate of the third series-connected transistor (17) being further connected to its drain, the source of the third p-channel current mirror transistor (15) being connected to the drain of the first p-channel current mirror transistor (19), the source of the fourth p-channel current mirror transistor (21) being connected to the drain of the second p-channel current mirror transistor (20);
- third and fourth n-channel current mirror transistors (28, 30) having their commonly connected gates connected to the drain of the third n-channel current mirror transistor (28), the drain of the third n-channel current mirror transistor (28) being further connected to the drain of the third p-channel current mirror transistor (15), the drain of the fourth n-channel current mirror transistor (30) being connected to a first plate of a first capacitor (50), a second plate of the first capacitor (50) being coupled to the drain of the fourth p-channel current mirror transistor (21);
- fifth and sixth n-channel current mirror transistors (29, 31) having their commonly connected gates connected to the drain of the fifth n-channel current mirror transistor (29), the drain of the fifth n-channel current mirror transistor (29) being further connected to the source of the third n-channel current mirror transistor (28), the sources of the fifth and sixth n-channel current mirror transistors (29, 31) being commonly connected to the negative power supply, the drain of the sixth n-channel current mirror transistor (31) being connected to the source of the fourth n-channel current mirror transistor (30), the second plate of the first capacitor (50) being coupled to the source-drain connection between the fourth and sixth n-channel current mirror transistors (30, 31);
- a p-channel pull-up transistor (150) having its source connected to the positive power supply, its gate connected to the drain-source connection between the second p-channel current mirror transistor (20) and the fourth p-channel current mirror transistor (21), and its drain connected to an output node (120);
- a n-channel pull-down transistor (160) having its source connected to the negative power supply, its gate connected to the source-drain connection between the fourth and sixth n-channel current mirror transistors (30, 31), and its drain connected to the output node (120);
- a second capacitor (47) having a first plate connected to the gate of the pull-up transistor (150) and to the first plate of the first capacitor (50);
- and having a second plate coupled to the output node (120) via a second resistive element (49);
- and
- a third capacitor (48) having a first plate connected to the gate of the pull-down transistor (160) and a second plate coupled to the output node (120) via the second resistive element (49).