Programmable current source correction circuit

A programmable current source correction circuit for correcting transistor current mismatch due to process variation, comprising:

• (A) a data storage means for storing correction information;
• (B) a first current division circuit for establishing a reference current, said first current division circuit further comprises:
• a first n-channel transistor and a first p-channel transistor, said first n-channel transistor having a gate coupled to a reference-bias voltage, a source coupled to a common ground, and a drain coupled to a drain of said first p-channel transistor, said first p-channel transistor having a gate coupled to its drain, and a source coupled to a high potential, said reference-bias voltage being the same as that being applied to the current sources being corrected;
• a second n-channel transistor and a second p-channel transistor, said second n-channel transistor having a source coupled to the common ground, a gate coupled to its drain, and the drain coupled to a drain of said second p-channel transistor, said second p-channel transistor having a gate coupled to the drain of said first n-channel transistor, and a source coupled to the high potential;
• (C) a programmable correction current circuit for establishing the amount of correction current required, said programmable correction current circuit further comprises:
• a third p-channel transistor, a first, second and third plurality of n-channel transistors, said third p-channel transistor having a source coupled to the high potential, a gate coupled to its drain, and the drain coupled to said first plurality of n-channel transistors' drains, said first plurality of n-channel transistors being switches and having their sources coupled to respective ones of said second plurality of n-channel transistors' drains, and having their gates coupled to a plurality of inputs for receiving information from said data storage means, said information indicating which of said first plurality of n-channel transistors are to be turned on, said second plurality of n-channel transistors being also switches and having their gates coupled to a first input, and their sources coupled to respective ones of plurality said third plurality of n-channel transistors' drains, said first input turning said second plurality of n-channel transistors on when high and off when low, said third plurality of n-channel transistors being binary weighted current sources and having their gates coupled to the drain of the second n-channel transistor, and their sources coupled to the common ground;
• (D) a second current division circuit for further reducing said reference current into smaller resolution, said second current division circuit further comprises:
• a fourth p-channel transistor and a third n-channel transistor, said fourth p-channel transistor having a source coupled to the high potential, a gate coupled to the drain of said third p-channel transistor, and a drain coupled to a drain of said third n-channel transistor, said third n-channel transistor having a gate coupled to its drain, and a source coupled to the common ground;
• a fifth and sixth p-channel transistors and a fourth and fifth n-channel transistors, said fifth p-channel transistor having a source coupled to the high potential, a gate coupled to the drain of said third p-channel transistor, and a drain coupled to a drain of said fourth n-channel transistor, said fourth n-channel transistor having a gate coupled to its drain, and a source coupled to the common ground, said sixth p-channel transistor having a source coupled to the high potential, a gate coupled to its drain, and the drain coupled to a drain of said fifth n-channel transistor, said fifth n-channel transistor having a gate coupled to the drain of said fifth p-channel transistor, and a source coupled to the common ground;
• and
• (E) a source-sink controlling circuit for controlling the mode of operation, said source-sink controlling circuit further comprises:
• a seventh and eighth p-channel transistors and a sixth and seventh n-channel transistors, said seventh p-channel having a source coupled to the high potential, a gate coupled to the drain of said sixth p-channel transistor, and a drain coupled to an input-output node, said input-output node being coupled to the current source being corrected, said eighth p-channel transistor having a source coupled to the high potential, a drain coupled to the drain of said sixth p-channel transistor, and a gate coupled to a second input, said second input turning said eighth p-channel transistor on when low and off when high, said sixth n-channel transistor having a drain coupled to the drain of said third n-channel transistor, a source coupled to the common ground, and a gate coupled to a third input, said third input turning said sixth n-channel transistor on when high and off when low, a said seventh n-channel transistor having a gate coupled to the drain of said third n-channel transistor, a source coupled to the common ground, and a drain coupled to the input-output node, said mode of operation being a sink when both said second and third inputs being low and being a source when both said second and third inputs being high.