Logarithmic intermediate frequency amplifier circuit operable on low voltage

A logarithmic intermediate frequency amplifier circuit comprising first through M-th intermediate frequency amplifiers which are connected in cascade, where M represents a positive integer greater than unity, the first one of the cascaded amplifiers receiving an input signal and the last one of the cascaded amplifiers providing an amplified output signal, first through M-th double balanced differential circuits each of which is connected to each of said first through said M-th intermediate frequency amplifiers, and an adding circuit connected to said first through said M-th double balanced differential circuits for adding outputs of said first through said M-th double balanced differential circuits and for providing a logarithmic output signal, each of said first through said M-th intermediate frequency amplifiers comprising an intermediate differential circuit which is supplied with an intermediate differential input and which produces an intermediate differential output, each of said first through said M-th double balanced differential circuits comprising:

• a primary differential circuit comprising a primary differential pair of transistors, both of said transistors of said primary differential pair of transistors being one of NPN and PNP types and which are connected to first and second input terminals and a first constant current source supplying a first current, said primary differential circuit receiving a first differential input from said intermediate differential input of a corresponding intermediate frequency amplifier through said first and said second input terminals and producing a first differential output;
• a secondary differential circuit comprising a secondary differential pair of transistors, both of transistors of said secondary differential pair of transistors being the other one of said NPN and said PNP types and which are connected to third and fourth input terminals receiving said intermediate differential output from said corresponding intermediate frequency amplifier and a second constant current source supplying a second current;
• and
• a tertiary differential circuit comprising a tertiary differential pair of transistors, both of said transistors of said tertiary differential pair of transistors being the other one of said NPN and said PNP types and which are connected to said third and said fourth input terminals receiving said intermediate differential output from said corresponding intermediate frequency amplifier and a third constant current source supplying a third current;
• said first differential output of said primary differential pair of transistors being connected to each of said second and said third constant current sources and delivering said first differential output to said secondary and said tertiary differential circuits so as to reduce said second and said third currents, said secondary and said tertiary differential circuits cooperatively producing a second differential output through first and second output terminals as one of said outputs of said first through said M-th double balanced differential circuits.