US 5,475,326 AGranted

Phase synchronization circuit having a short pull-in time and a low jitter

AssigneeNEC Corporation

InventorKazuaki Masuda

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Abstract

In a phase synchronization circuit including a digital phase comparator, a synchronism discrimination circuit, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a frequency-division circuit, the charge pump circuit comprises a level comparator comparing the output voltage of the loop filter with a predetermined reference voltage, for outputting a level discrimination signal, a first AND circuit for outputting a logical product of an output UP of the phase comparator and the level discrimination signal, an inverter for outputting an inverted signal of an output DOWN of the phase comparator, and a second AND circuit for outputting a logical product of an output signal of the inverter and the level discrimination signal. A PMOS transistor is connected at its source to a voltage supply through a constant current source, and has its gate applied with an output signal of the AND circuit, and its drain connected to an input of the loop filter, and an NMOS transistor is connected at its drain to the input of the loop filter and has its gate applied with an output signal of the AND circuit and its source connected to ground through a constant current source.

Claims3

Dependent claims

A phase synchronization circuit which includes

a digital phase comparator receiving a predetermined input signal at a first input,
a synchronism discrimination circuit receiving an output of said phase comparator, for discriminating a phase synchronization condition so as to output a control signal,
a charge pump circuit receiving the output of said phase comparator, and controlled by said control signal, for outputting a phase differential signal,
a loop filter receiving said phase differential signal of said charge pump circuit, for limiting a frequency band of said phase differential signal,
a voltage controlled oscillator frequency-controlled by an output voltage of said loop filter for providing an output signal at an output terminal;
and
a frequency-division-circuit receiving said output signal of said voltage controlled oscillator, for frequency-dividing said output signal of said voltage controlled oscillator and for feeding back a frequency-divided output signal to a second input of said phase comparator,
characterized in that said charge pump comprises:
a level comparator receiving said output voltage of said loop filter for comparing it with a predetermined reference voltage so as to output a predetermined level discrimination signal,
a first AND circuit receiving a first output signal of said phase comparator and said level discrimination signal, for outputting a logical product signal,
an inverter receiving a second output signal of said phase comparator for outputting an inverted signal of said second output signal,
a second AND circuit receiving said inverted signal outputted from said inverter and said level discrimination signal, for outputting a logical product signal,
a PMOS transistor having its source connected to a voltage supply through a first constant current source, its gate connected to receive an output signal of said first AND circuit, and its drain connected to an input of said loop filter, and
an NMOS transistor having its drain connected to said input of said loop filter, its gate connected to receive an output signal of said second AND circuit, and its source connected to ground through a second constant current source,
a current value of said first constant current source being controlled by said control signal outputted from said synchronism discrimination circuit and said level discrimination signal, and
a current value of said second constant current source being controlled by said control signal outputted from said synchronism discrimination circuit.

13 more elements

A phase synchronization circuit which includes

a digital phase comparator receiving a predetermined input signal at a first input,
a synchronism discrimination circuit receiving an output of said phase-comparator, for discriminating a phase synchronization condition so as to output a control signal,
a charge pump circuit receiving the output of said phase comparator, and controlled by said control signal, for outputting a phase differential signal,
a loop filter receiving said phase differential signal of said charge pump circuit, for limiting a frequency band of said phase differential signal,
a voltage controlled oscillator frequency-controlled by an output voltage of said loop filter for providing an output signal at an output terminal, and
a frequency-division circuit receiving said output signal of said voltage controlled oscillator, for frequency-dividing said output signal of said voltage controlled oscillator and for feeding back a frequency-divided output signal to a second input of said phase comparator,
characterized in that said charge pump comprises:
a first level comparator receiving said output voltage of said loop filter for comparing it with a first predetermined reference voltage so as to output a first predetermined level discrimination signal,
a second level comparator receiving said output voltage of said loop filter for comparing it with a second predetermined reference voltage so as to output a second predetermined level discrimination signal,
an AND circuit receiving a first output signal of said phase comparator and said first level discrimination signal, for outputting a logical product signal,
a first OR circuit receiving an output signal of said AND circuit and said second level discrimination signal, for outputting a logical sum signal,
an inverter receiving a second output signal of said phase comparator for outputting an inverted signal of said second output signal,
a second OR circuit receiving an output signal of said inverter and said second level discrimination signal, for outputting a logical sum signal,
a PMOS transistor having its source connected to a voltage supply through a first constant current source, its gate connected to receive an output signal of said first OR circuit, and its drain connected to an input of said loop filter, and
an NMOS transistor having its drain connected to said input of said loop filter, its gate connected to receive an output signal of said second OR circuit, and its source connected to ground through a second constant current source,
a current value of said first constant current source being controlled by said control signal outputted from said synchronism discrimination circuit and said first level discrimination signal, and,
a current value of said second constant current source being controlled by said control signal outputted from said synchronism discrimination circuit and said second level discrimination signal.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/317,531Filed 4 Oct 1994
Priority: JP 5-2476624 Oct 1993
Granted: 12 Dec 1995
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03L 7/18
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop:…
H03L 7/0898
Details of the current generators: the source or sink current values being variable
H03L 7/10
Details of the phase-locked loop: for assuring initial synchronisation or for broadening the capture range
H03L
Automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or