Programmable logic device having input transition detector circuit

A semiconductor integrated circuit comprising:

• a first circuit for outputting a pulse signal in response to a control signal and a change in a signal output from one of an output pin and an input/output pin;
• a second circuit which is set in an enable state in response to the pulse signal;
• and
• a third circuit which is programmable for controlling whether or not the pulse signal output from said first circuit is transmitted to said second circuit by outputting the control signal to said first circuit.

A programmable logic device comprising:

• an AND array to which an input signal is supplied;
• a first input transition detector (ITD) circuit for outputting a first pulse signal upon detection of a level change in the input signal;
• a first sense amplifier circuit for reading out data from said AND array;
• an OR array to which an output signal from said first sense amplifier is supplied;
• a second sense amplifier circuit for reading out data from said OR array, an output of said second sense amplifier coupled to an input of said AND array;
• a second ITD circuit for outputting a second pulse signal upon detection of a level change in an output signal from said second sense amplifier;
• logic means for activating said first sense amplifier circuit and said second sense amplifier circuit in response to the first pulse signal output from said first ITD circuit and the second pulse signal output from said second ITD circuit;
• and
• control means for controlling said logic means such as to deactivate said first sense amplifier circuit and said second sense amplifier circuit when the output signal of said second sense amplifier circuit is not fed back to said AND array.

A programmable logic device comprising:

• an AND array to which an input signal is supplied;
• a first ITD circuit for outputting a first pulse signal upon detection of a level change in said input signal;
• a sense amplifier circuit for reading out data from said AND array;
• a fixed OR circuit to which an output signal from said sense amplifier circuit is supplied;
• a macrocell to which data output from said fixed OR circuit is supplied, an output of said macrocell coupled to an input of said AND array;
• a second ITD circuit for outputting a second pulse signal upon detection of a level change in an output signal from said macrocell;
• logic means for activating said sense amplifier circuit in response to the first pulse signal output from said first ITD circuit and the second pulse signal output from said second ITD circuit;
• and
• control means for controlling said logic means so as to deactivate said sense amplifier circuit when the output signal of said macrocell is not fed back to said AND array.

A programmable logic device comprising:

• an AND array having a programmable product term line and supplied with an input signal;
• a first ITD circuit supplied with said input signal and outputting a first pulse signal upon detection of a level change in said input signal;
• a first sense amplifier circuit for amplifying an output signal from said AND array;
• an OR array having a programmable sum term line and supplied with an output signal from said first sense amplifier circuit;
• a second sense amplifier circuit for amplifying and outputting an output signal from said OR array;
• a feedback circuit for coupling an output from said second sense amplifier circuit to an input of said AND array;
• a second ITD circuit for outputting a second pulse signal upon detection of a level change in an output signal from said second sense amplifier circuit;
• a control circuit for outputting a control signal as to whether or not the output signal from said second sense amplifier circuit will be fed back to said AND array by said feedback circuit;
• and
• a logical circuit for, in response to the control signal output from said control circuit, setting said first and second sense amplifier circuits in an enable state for a time period during which the first and second pulse signals are output from said first and second ITD circuits, when the output signal from said second sense amplifier is fed back to said AND array, and setting said first and second sense amplifier circuits in an enable state for a period of time during which the first pulse signal is output from said first ITD circuit, when the output signal from said second sense amplifier circuit is not fed back to said AND array.

A programmable logic device comprising:

• an AND array having a programmable product term line and supplied with an input signal;
• a first ITD circuit supplied with the input signal and outputting a first pulse signal upon detection of a level change in said input signal;
• a sense amplifier circuit for amplifying an output signal from said AND array;
• a fixed OR circuit supplied with an output signal from said sense amplifier circuit;
• a macrocell supplied with an output signal from said fixed OR circuit;
• a feedback circuit for coupling an output of said macrocell to an input of said AND array;
• a second ITD circuit for outputting a second pulse signal upon detection of a change in an output signal of said macrocell;
• a control circuit for outputting a control signal as to whether or not the output signal of said macrocell is fed back to said AND array by said feedback circuit;
• and
• a logical circuit for, in response to the control signal from said control circuit, setting said sense amplifier circuit in an enable state for a time period during which the first and second pulse signals are output from said first and second ITD circuits, when the output from said macrocell is fed back to said AND array, and setting said sense amplifier in an enable state for a time period during which the first pulse signal is output to said first ITD circuit, when the output signal from said macrocell is not fed back to said AND array.

A programmable logic device comprising:

• an AND array to which an input signal is supplied;
• a first ITD circuit for outputting a first pulse signal upon detection of a level change in the input signal;
• a first sense amplifier circuit for reading out data from said AND array;
• an OR array to which an output signal from said first sense amplifier circuit is supplied;
• a second sense amplifier circuit for reading out data from said OR array;
• a macrocell to which data is output from said second sense amplifier, said macrocell having an output coupled to an input of said AND array;
• a second ITD circuit for outputting a second pulse signal upon detection of a level change in an output signal from said macrocell;
• logic means for activating said first sense amplifier circuit and said second sense amplifier circuit in response to the first pulse signal output from said first ITD circuit and the second pulse signal output from said second ITD circuit;
• and
• control means for controlling said logic means such as to deactivate said first sense amplifier circuit and said second sense amplifier circuit when the output signal of said macrocell is not fed back to said AND array.

A programmable logic device comprising:

• an AND array having a programmable product term line and supplied with an input signal;
• a first ITD circuit supplied with said input signal and outputting a first pulse signal upon detection of a level change in said input signal;
• a first sense amplifier circuit for amplifying an output signal from said AND array;
• an OR gate array having a programmable sum term line and supplied with an output signal from said first sense amplifier circuit;
• a second sense amplifier circuit for amplifying and outputting an output signal from said OR array;
• a macrocell to which data is output from said second sense amplifier circuit;
• a feedback circuit for coupling an output from said macrocell to an input of said AND array;
• a second ITD circuit for outputting said second pulse signal upon detection of a level change in an output signal from said macrocell;
• a control circuit for outputting a control signal as to whether or not the output signal from said macrocell will be fed back to said AND array by said feedback circuit;
• and
• a logical circuit for, in response to the control signal output from said control circuit, setting said first and second sense amplifier circuits in an enable state for a time period during which the first and second pulse signals are output from said first and second ITD circuits, when the output signal from said macrocell is fed back to said AND array, and setting said first and second sense amplifier circuits in an enable state for a time period during which the first pulse signal is output from said first ITD circuit, when the output signal from said macrocell is not fed back to said AND array.

A programmable logic device comprising:

• an AND array to which an input signal is supplied;
• a first ITD circuit for outputting a first pulse signal upon detection of a level change in said input signal;
• a sense amplifier circuit for reading out said data from said AND array;
• a fixed OR circuit to which an output signal from said sense amplifier is supplied, said fixed OR gate having an output coupled to an input of said AND array;
• a second ITD circuit for outputting a second pulse signal upon detection of a level change in an output signal from said fixed OR array;
• logic means for activating said sense amplifier circuit in response to the first pulse signal output from said first ITD circuit and the second pulse signal output from said second ITD circuit;
• and
• control means for controlling said logic means so as to deactivate said sense amplifier circuit when the output signal of said fixed OR circuit is not fed back to said AND array.

A programmable logic device comprising:

• an AND array having a programmable product term line and supplied with an input signal;
• a first ITD circuit supplied with an input signal and outputting a first pulse signal upon detection of a level change in said input signal;
• a sense amplifier circuit for amplifying an output signal from said AND array;
• a fixed OR circuit supplied with an output signal from said first sense amplifier circuit;
• a feedback circuit for coupling an output of said fixed OR circuit to an input of said AND array;
• a second ITD circuit for outputting a second pulse signal upon detection of a change in an output signal of said fixed OR circuit;
• a control circuit for outputting a control signal as to whether or not the output signal of said fixed OR circuit is fed back to said AND array by said feedback circuit;
• and
• a logical circuit for, in response to the control signal output from said control circuit, setting said sense amplifier circuit in an enable state for a time period during which the first and second pulse signals are output from said first and second ITD circuits, when the output signal from said fixed OR circuit is fed back to said AND array, and setting said sense amplifier circuit in an enable state for a time period during which the first pulse signal is output from said first ITD circuit, when the output signal from said fixed OR circuit is not fed back to said AND array.