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US 5,475,261 AGranted
Semiconductor device having many lead pins
AssigneeFujitsu Limited
InventorTetsu Tanizawa
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a predetermined number of surface mount first lead pins (14), arranged around the periphery of the underside of a package (13) fitted with a chip (11). A predetermined number of second lead pins (22, 41), each having a specific function, are provided in a region near the center of the underside of the package (13) inside of the region populated with the first lead pins (14).
Claims13
A semiconductor device comprising;
- a predetermined number of surface mount first lead pins arranged in a region around the periphery of an underside of a package, said package having a chip attached thereto;
- and
- a plurality of surface mount second lead pins provided in a center region of the underside of said package inside of the region containing said first lead pins;
- said second lead pins being arranged in a plurality of spaced groups, each of said groups having a specific function and being comprised of a plurality of said second lead pins and the distance between adjacent groups being greater than the distance between the second lead pins in any one of said groups.
1 more element
A semiconductor device comprising:
- a predetermined number of surface mount first lead pins arranged in a region around the periphery of an underside of a package fitted with a chip;
- a first thin film built in layers of patterned film for connecting said chip and said first lead pins, said first thin film being positioned inside said package and said chip being connected to said first lead pins through said first thin film;
- and
- at least one second lead pin having a specific function and connected to said chip without being connected through said first thin film, said second lead pin being located near a center region inside of the region populated with said first lead pins.
1 more element
A semiconductor device comprising:
- a predetermined number of surface mount first lead pins arranged in a region around the periphery of an underside of a package fitted with a chip;
- a first thin film built in layers of patterned film for connecting said chip and said first lead pins;
- at least one second lead pin having a specific function and connected to said chip through said first thin film, said second lead pin being located near a center region inside of the region populated with said first lead pins;
- and wherein said first thin film is positioned inside said package and said chip is connected to said first lead pins and said at least one second lead pin through said first thin film.
1 more element
A semiconductor device comprising:
- a predetermined number of surface mount first lead pins arranged in a region around the periphery of an underside of a package fitted with a chip;
- and
- a plurality of surface mount second lead pins (22), each having a specific function and provided in a region near a center region of the underside of said package inside of the region populated with said first lead pins, at least two of said second lead pins being assigned to each specific function of said second lead pins;
- and
- at least one terminal having a specific function and located within the region of said second lead pins, said terminal being longer than said first lead pins whereby when the device is mounted on a board said terminal extends through said board and is fixed thereto.
2 more elements
A semiconductor device comprising:
- a predetermined number of surface mount first lead pins arranged in a region around the periphery of an underside of a package fitted with a plurality of chips;
- a first thin film built in layers of patterned film for connecting said chips and said first lead pines;
- at least one second lead pin having a specific function and connected to said chips without being connected through said thin film, said second lead pin being located near a center region inside of the region populated with said first lead pins;
- and
- a second thin film connecting said chips.
2 more elements
Dependencies are inferred from the claim text.