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US 5,474,944 AGranted
Process for manufacturing integrated circuit with power field effect transistors
AssigneesSGS-Thomson Microelectronics S.A., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
InventorRaffaele Zambrano
Life of this patent
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Abstract
A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.
Claims33
A method for fabricating vertical-current-flow field-effect transistors, comprising the steps of:
- (a.) providing a monolithic semiconductor surface having a first conductivity type;
- (b.) forming patterned second-conductivity-type diffusions in deep body locations therein;
- (c.) forming a thin film of a first material over said surface, and a thin film of a second material over said first material;
- (d.) implanting said semiconductor surface, through apertures in a photoresist layer and said second material, with second-conductivity-type dopants, to form body regions;
- (e.) etching said first material to form apertures corresponding to said apertures in said photoresist layer;
- (f.) implanting said semiconductor surface, through said apertures in said first and second materials, with first-conductivity-type dopants, to form source regions;
- said implanting step (f.) being performed with a stopping distance which is less than half the stopping distance of said implanting step (d.), whereby said first-conductivity-type dopants reach into said semiconductor surface only in locations of said apertures in said first and second materials;
- (g.) oxidizing said first surface, to form an insulating layer which is thicker over at least a portion of said source regions than elsewhere;
- and
- (h.) after said steps (a.)-(g.), forming insulated gate regions on said first surface which are each capacitively coupled to at least some portion of said body region at said first surface;
- and making contact to said source regions.
8 more elements
A method for fabricating vertical-current-flow field-effect transistors, comprising the steps of:
- (a.) providing a substrate which includes at least one substantially monolithic body of semiconductor material having a first conductivity type in proximity to a first surface thereof;
- (b.) forming patterned second-conductivity-type diffusions in deep body locations;
- (c.) forming a thin film of a first material which is different from said semiconductor material on said first surface, and a thin film of a second material which is different from said first material over said first material;
- (d.) depositing and photolithographically patterning photoresist, to form apertures over central portions of body locations;
- (e.) selectively etching said second material under said apertures, to form corresponding apertures in said second material while leaving said first material substantially intact;
- (f.) implanting said first surface, through said apertures in said photoresist, with second-conductivity-type dopants, to form body regions;
- (g.) removing said photoresist;
- (h.) etching said first material under said apertures in said second material, to form corresponding apertures in said first material;
- (i.) implanting said first surface, through said apertures in said first and second materials, with first-conductivity-type dopants, to form source regions;
- said implanting step (i.) being performed with a stopping distance which is less than half the stopping distance of said implanting step (f.), whereby said first-conductivity-type dopants reach into said semiconductor surface only in locations of said apertures in said first and second materials;
- (j.) oxidizing said first surface, to form an insulating layer which is thicker over at least a portion of said source regions than elsewhere;
- (k.) after said steps (a.)-(j.), forming insulated gate regions on said first surface which are each capacitively coupled to at least some portion of said body region at said first surface;
- and
- (l.) making contact to said source regions.
11 more elements
A method for fabricating vertical-current-flow field-effect transistors, comprising the steps of:
- (a.) providing a substrate which includes at least one substantially monolithic body of semiconductor material having a first conductivity type in proximity to a first surface thereof;
- (b.) forming patterned second-conductivity-type diffusions in locations corresponding to deep body areas of vertical-current-flow field-effect transistors;
- (c.) forming a patterned layer of field isolation oxide, on said first surface, which has apertures, in locations corresponding to active areas of vertical-current-flow field-effect transistors, exposing said first surface;
- (d.) forming a thin film of a first material which is different from said semiconductor material on said first surface, and a thin film of a second material which is different from said first material over said first material;
- (e.) depositing and photolithographically patterning photoresist, to form apertures over central portions of body locations;
- (f.) selectively etching said second material under said apertures, to form corresponding apertures in said second material while leaving said first material substantially intact;
- (g.) implanting said first surface, through said apertures in said photoresist, with first-conductivity-type dopants, to form body regions;
- (h.) removing said photoresist;
- (i.) etching said first material under said apertures in said second material, to form corresponding apertures in said first material;
- (j.) implanting said first surface, through said apertures in said first and second materials, with first-conductivity-type dopants, to form source regions;
- said implanting step (j.) being performed with a stopping distance which is less than half the stopping distance of said implanting step (g.), whereby said first-conductivity-type dopants reach into said semiconductor surface only in locations of said apertures in said first and second materials;
- (k.) oxidizing said first surface, to form an insulating layer which is thicker over at least a portion of said source regions than elsewhere;
- (l.) stripping said first and second materials, and growing a gate oxide over exposed portions of said surface;
- (m.) depositing and patterning a first additional thin film of conductive material to form gate regions;
- (n.) etching away said thicker oxide over at least some portions of said source regions;
- and
- (o.) depositing and patterning a second additional thin film of conductive material to make contact to said source regions.
14 more elements
Dependencies are inferred from the claim text.