Fault-tolerant computer system with hidden local memory refresh
AssigneeTandem Computers Incorporated
InventorRichard A. Vrba
Life of this patent
Estimating the term…
Abstract
A fault tolerant computer system having a plurality of processor modules having independent clocks for processing an instruction stream, global memory accessible by all of the processor modules, and a local memory configured within each processor module and clocked synchronously therewith. The local memory is periodically refreshed between accesses to the local memory by the processor. Warning signals indicating a potential access to the local memory are provided to a refresh controller and the local memory is refreshed or the refresh is aborted depending upon the number of clock cycles available before a local memory access occurs. A speculative refresh may be stalled until a processor instruction is decoded to determine whether a local memory access is requested or not.
Claims19
A fault tolerant computer system for processing an instruction stream, comprising:
- a plurality of processor modules, each of said processor modules executing said instruction stream, each processor module having:
- a processor for executing said instructions;
- an independent clock for providing clock cycles for controlling execution of said instruction stream independently of said other processor modules;
- a local memory coupled to said processor so as to be accessible thereby, wherein said local memory is of the type storing data in a dynamic manner and requiring periodic refresh to maintain data integrity;
- and
- local memory refresh control means for controlling said local memory refreshes such that said refreshes only occur when said processor is not requesting access to said local memory.
A refresh controller for use with a computer system having a processor, a dynamic memory accessed by said processor, said processor issuing access requests prior to accessing said dynamic memory, and wherein said dynamic memory is of the type requiring periodic refreshes to maintain the integrity of data stored therein, and a clock for providing clock cycles, comprising:
- a refresh timer receiving said clock cycles and issuing a refresh request signal at predetermined refresh intervals;
- access warning means for receiving a request from said processor and providing a warning signal in response thereto;
- and
- refresh timing control means, coupled to said refresh timer and warning means and receiving said refresh request signal and said warning signal, for initiating a dynamic memory refresh in response to said refresh request signal and for stalling said refresh for a predetermined number of clock cycles in response to said warning signal.
An apparatus for controlling the refresh of a dynamic random access memory employed in a computer system having a processor, periodically accessing said dynamic random access memory and issuing memory access requests prior to such accessing, comprising:
- means for issuing a refresh request at predetermined refresh intervals;
- means for initiating a dynamic memory refresh in response to said refresh request signal;
- means for receiving a request for access to said dynamic memory from said processor and providing a warning signal in response thereto;
- and
- means for stalling said refresh for a predetermined number of clock cycles in response to said warning signal.
A fault tolerant computer system for processing an instruction stream, comprising:
- first, second and third processors of substantially identical configuration, said first, second and third processors having independent clocks providing independent clock cycles, each of said processors periodically issuing a command;
- first, second and third local memories respectively clocked synchronously with said first, second and third processors and accessible thereby, wherein said first, second and third local memories are of the dynamic type requiring periodic refresh to maintain data integrity of data stored therein;
- wherein said first, second and third processors issue one of a plurality of commands, wherein execution of predetermined ones of the plurality of commands involves accessing at least one of said first, second and third local memories;
- and
- first, second and third local memory refresh control means for periodically initiating a speculative local memory refresh operation and for, in response to said issued processor command, stalling said speculative local memory refresh for a predetermined period of time.
Dependencies are inferred from the claim text.