Clock generator

A clock generator comprising:

• a selector for selecting one of a plurality of clock signals;
• a first delay element for delaying a hardware reset signal by a predetermined time;
• a clock source selection register for receiving a clock source selection value setting pulse for writing set value data in said clock source selection register, said clock source selection register holding said set value data for designating one of said clock signals to be selected and receiving as a reset input the delayed hardware reset signal through said first delay element;
• a second delay element for delaying said clock source selection value setting pulse;
• a first flip-flop for receiving as a clock input the delayed clock source selection value setting pulse through said second delay element, and responsive to an OR signal of a software reset signal and said hardware reset signal to generate a "Low" level output signal;
• a second flip-flop for receiving as a clock input an AND signal of the output signal of said selector and said hardware reset signal, and receiving as data input an OR signal of the inversion of its own output signal and the "Low" level output signal of said first flip-flop;
• and
• said second flip-flop having an input terminal to which is input a power-on reset signal for independently setting said second flip-flop.