Method and apparatus for asynchronously stopping the clock in a processor

A computer system including:

• a means for generating an oscillating analog signal;
• means for multiplying said oscillating analog signal by a predetermined factor to produce a clock signal;
• a data processor having a first portion operating synchronous with said clock signal, said data processor including a means for executing a program consisting of a sequence of instructions having boundaries;
• and means coupled to said execution means for halting said program on an instruction boundary and decoupling said clock signal from said first portion of said data processor.

A microprocessor comprising:

• a central processing unit (CPU) core;
• a clock input coupled to receive an oscillating analog signal;
• a phase-locked loop circuit multiplying said oscillating analog signal by a predetermined factor to produce an internal clock signal coupled to said CPU core;
• a plurality of inputs for receiving a corresponding plurality of interrupt signals, including a stop signal;
• a microcode engine having an input coupled to receive said stop signal and an output bit, said microcode engine executing a program comprising a set of instructions having boundaries, each instruction including one or more microinstructions, said microcode engine also including a microcode routine which executes in response to said stop signal, said microcode routine placing said microprocessor into a known state, then setting said output bit;
• a prioritizer coupled to said microcode engine and to said plurality of interrupt inputs for granting a priority status to said plurality of interrupt signals and for signaling said microcode engine to suspend execution of said computer program on a next instruction boundary in response thereto, said stop signal being granted a high priority interrupt status among said plurality of interrupt signals;
• logic means for decoupling said internal clock signal from said CPU core in response to said stop signal and said output bit.

A method of masking a clock signal from at least a portion of a microprocessor comprising the steps of:

• (a) providing an interrupt indicating that said clock signal is to be masked in response to the assertion of an external pin of said microprocessor;
• (b) executing a routine within a microcode engine of said microprocessor in response to said interrupt to place said microprocessor in a known state;
• and
• (c) signaling by said microcode engine to a logic circuit to assert a signal to mask said clock signal from said at least a portion of said microprocessor.

A microprocessor comprising:

• means for generating an internal clock signal from an external oscillatory analog signal, the internal clock signal being provided to first and second portions of the microprocessor;
• an execution unit which executes a stream of instructions synchronous to the internal clock signal, the instructions in the stream being separated by boundaries, at least one of the instructions requiring more than one period of the internal clock signal to complete execution, the execution unit storing a microcode routine which, when executed, places the microprocessor in a known state and then sets an internal bit;
• an external pin for receiving a stop signal during execution of a current instruction and asynchronous to the internal clock signal;
• interrupt means coupled to the execution unit and to the external pin, the interrupt means for responding to the stop signal by signaling the execution unit to execute the microcode routine, the microcode routine setting the internal bit on a next boundary of the current instruction;
• logic means coupled to the execution unit, the interrupt means, and the internal clock signal for masking the internal clock signal to the first portion of the microprocessor, but not to the second portion of the microprocessor, in response to the internal bit.

A method of operating a microprocessor coupled to receive an external oscillatory signal, the microprocessor having first and second portions, the method comprising the steps of:

• (a) generating an internal clock signal from the external oscillatory signal, the internal clock signal being coupled to the first and second portions of the microprocessor;
• (b) receiving an external stop signal coupled to the microprocessor, the external stop signal being received asynchronous to the internal clock signal;
• (c) halting the execution of a current instruction which is part of a stream of instructions having boundaries, at a next instruction, boundary in response to the external stop signal;
• (d) masking the internal clock signal from the first portion of the microprocessor in response to the external stop signal;
• and
• (e) continuing to couple the internal clock signal to the second portion of the microprocessor.