Multilevel instruction cache
AssigneeNorth American Philips Corporation
InventorChi-Hung Chi
Life of this patent
Estimating the term…
Abstract
A cache memory for use between a processing unit and a main memory includes a prefetch buffer, a use buffer, and a head buffer. The prefetched buffer is a FIFO or LRU register which prefetches instructions from contiguous memory locations after the address specified by the program counter. The head buffer is a FIFO or LRU register which is utilized to store instructions from the tops of the program blocks which are accessed from main memory following recent cache misses. The use buffer is a relatively large, inexpensive buffer, preferably a directly mapped buffer, which stores recent hits from the prefetched buffer as well as selected instructions from main memory following cache misses.
Claims31
A cache memory system for implementing the transfer of instruction codes from a main memory to a processing unit, said processing unit including a program counter the contents of which specify an address in the main memory which contains a next instruction code to be executed by said processing unit, comprising:
- prefetch buffer means connected to prefetch and store instruction codes from addresses in the main memory which sequentially follow the addresses contained in the program counter;
- a head buffer;
- a use buffer;
- and
- instruction transfer control means responsive to the contents of the program counter, the prefetch buffer means, the head buffer, and the use buffer, which function so that:
- a) if an instruction code specified by the program counter is in the prefetch buffer, said code is transmitted to the processing unit and is also stored in use buffer,
- b) if the instruction code specified by the program counter is in the head buffer or the use buffer, said code is transmitted to the processing unit;
- or
- c) if the instruction code specified by the program counter is not in any of the prefetch buffer means, the head buffer, or the use buffer, said code is fetched from the main memory, transmitted to the processing unit and also 1) stored in the head buffer if the contents of the program counter satisfy a predetermined test or 2) stored in the use buffer if the contents of the program counter do not meet the predetermined test.
A method for operating a computer for implementing the transfer of instruction codes from a main memory to a processing unit, said processing unit including a program counter the contents of which specify an address in the main memory which contains a next instruction code to be executed by said processing unit, comprising:
- providing a cache with a prefetch buffer, a head buffer and a use buffer;
- prefetching and storing in the prefetch buffer, instruction codes from addresses in the main memory which sequentially follow the addresses contained in the program counter;
- if an instruction code specified by the program counter is in the prefetch buffer, transmitting said code to the processing unit and also storing said code in the use buffer,
- if the instruction code specified by the program counter is in the head buffer or the use buffer, transmitting said code to the processing unit;
- if the instruction code specified by the program counter is not in any of the prefetch buffer, the head buffer, and the use buffer, fetching said code from the main memory, transmitting said code to the processing unit and also 1) storing said code in the head buffer if the contents of the program counter satisfy a predetermined test or 2) storing said code in the use buffer if the contents of the program counter do not meet the predetermined test.
A microprocessor integrated circuit including a cache memory system for implementing the transfer of instruction codes from a main memory which contains a next instruction code to be executed the processing unit, comprising:
- prefetch buffer means connected to prefetch and store instruction codes from addresses in the main memory which sequentially follow the addresses contained in the program counter;
- a head buffer;
- a use buffer;
- and
- instruction transfer control means responsive to the contents of the program counter, the prefetch buffer means, the head buffer and the user buffer, which function so that:
- a) if an instruction code specified by the program counter is in the prefetch buffer, the code is transmitted to the processing unit and is also stored in the use buffer,
- b) if the instruction code specified by the program counter is in the head buffer or the use buffer, the code is transmitted to the processing unit;
- or
- c) if the instruction code specified by the program counter is not in any of the prefetch buffer means, the head buffer or the use buffer, the code is fetched from the main memory, transmitted to the processing unit and also 1) stored in the head buffer if the contents of the program counter satisfy a predetermined test or 2) stored in the use buffer if the contents of the program counter do not meet the predetermined test.
Dependencies are inferred from the claim text.