Interrupt vector method and apparatus

An apparatus for processing a plurality of interrupts in a processor system, comprising:

• a plurality of interrupt vector registers containing a programmable interrupt vector;
• a plurality of interrupt trigger inputs corresponding to each of said interrupt vector registers;
• a multiplexer directly connected to said interrupt vector registers;
• control logic for controlling said multiplexer to select one of said interrupt vectors as said selected interrupt vector upon activation of a corresponding one of said interrupt triggers;
• a slot memory address counter receiving a selected interrupt vector through said multiplexer, said slot memory address being controlled by said control logic to load said selected interrupt vector;
• a sequencer slot memory addressed by said slot memory address counter, said sequencer slot memory containing addresses of a plurality of sequences of instructions stored in an instruction memory;
• an instruction address counter receiving addresses from said sequencer slot memory and providing addresses to said instruction memory;
• and
• sequencer control logic to load said instruction address counter from said sequencer slot memory according to said slot memory address counter, and to control execution of said sequences wherein,
• one of said sequences is executed upon activation of said one of said interrupt triggers, execution of said one of said sequences beginning at the address contained in one of said interrupt registers corresponding to said interrupt trigger, and addresses of said sequences in said sequencer slot memory are sequentially loaded into said instruction address counter until a stop bit is indicated in a word in said sequencer slot memory;
• said vector registers being configured to be written from a bus by devices with access to said bus.