I/O controller using single data lines for slot enable/interrupt signals and specific circuit for distinguishing between the signals thereof

A programmable logic controller comprising:

• a backplane board including a plurality of slots for receiving I/O modules therein;
• a central processing unit (CPU) situated on a CPU board coupled to said backplane board;
• a serial data bus situated on said backplane board for coupling said CPU to said slots;
• a plurality of slot enable lines respectively coupled to said plurality of slots;
• at least one I/O module being situated in one of said slots, said I/O module including an interrupt generating circuit for providing an interrupt to the slot enable line coupled to said I/O module, and
• an I/O communications master circuit, coupled to the CPU, for generating a plurality of enable drive signals on a plurality of enable drive lines, each enable drive signal exhibiting a first logic state to indicate that the CPU desires to access a particular I/O module in a particular slot, each enable drive signal otherwise exhibiting a second logic state, said I/O communications master circuit generating a different enable drive signal for each slot;
• an interrupt controller, coupled to the plurality of enable drive lines and said slot enable lines, said interrupt controller including
• slot enable signal generating means for receiving an enable drive signal on an enable drive line corresponding to a particular slot, and when said enable drive signal exhibits the first logic state, the slot signal generating means in response generates a slot enable signal on the respective slot enable line coupled to the particular slot thus indicating that the CPU desires to access the particular I/O module, and
• an AND circuit, coupled to the enable drive line corresponding to the particular slot and the respective slot enable line, for generating a CPU interrupt signal exhibiting a first logic value which indicates an interrupt from the particular I/O module when both the enable drive signal exhibits a logic value indicating that the CPU is not attempting to access the particular I/O module and the slot enable signal exhibits a value corresponding to an attempt by the particular I/O module to issue an interrupt, said AND circuit otherwise generating a CPU interrupt signal exhibiting a second logic value indicating no interrupt when the enable drive signal exhibits a logic value indicating that the CPU is attempting to access the particular I/O module.

A method of communicating with I/O modules situated in slots in a programmable logic controller (PLC), said PLC including a central processing unit (CPU) coupled to said modules by a serial data line therebetween and by an interrupt controller therebetween, said method comprising the steps of:

• providing a plurality of slot enable lines between said interrupt controller and said slots, each of said slot enable lines being dedicated to a respective slot;
• said interrupt controller supplying a slot enable signal at selected times to a particular slot enable line to enable the I/O module in the slot coupled to said particular slot enable line;
• said I/O module supplying an interrupt signal at selected times over the same slot enable line used by said interrupt controller to send the slot enable signal to said I/O module, and
• said interrupt controller performing an AND operation to determine if both a particular slot enable line coupled to a particular slot exhibits a logic state corresponding to an interrupt and said interrupt controller is not driving said particular slot enable line with a slot enable signal exhibiting a logic state which enables said particular slot, to ascertain that said interrupt controller is receiving an interrupt from said I/O module.