US 5,473,752 AGranted

Fault isolation circuit

AssigneeDetector Electronics Corporation

InventorsEdward G. Beistle, Martin J. Seabolt

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Abstract

A system for detecting and isolating faults in a two-wire communications loop which includes a number of node circuits dispersed along the loop. Each node circuit executes a fault detection algorithm and selectively switches its connections to adjacent node circuits to effectively isolate itself from the fault condition. When all node circuits have completed their respective fault detection algorithms the fault condition is disconnected from the two-wire communications loop.

Claims5

Dependent claims

An apparatus for detecting and isolating a fault condition in any of a plurality of node circuits, in a communications loop comprised of a plurality of said node circuits connected along a two-wire closed communications loop, wherein the respective ends of the closed loop are connected to a computer processor, and each node circuit may independently send data to and receive data from the processor via the communications loop, comprising:

a) each node circuit respectively having connections to a neuron circuit associated therewith, and each neuron circuit having means for connection to a data-originating circuit, and means for transferring data from said data-originating circuit to said node circuit;
b) each node circuit respectively having a fault switching circuit interposed between said two-wire communications loop and said neuron circuit, each said fault switching circuit further comprising:
i) a first switching state wherein said communications loop is unbroken and is connected to said neuron circuit associated with said respective node circuit;
ii) a second switching state wherein said communications loop is broken and a first broken end is terminated in a line resistance and a second broken end is connected to said neuron circuit;
iii) a third switching state wherein said communications loop is broken and a first broken end is connected to said neuron circuit and a second broken end is terminated in a line resistance;
and
iv) a fourth switching state wherein said communications loop is broken and both of said broken ends are each terminated in a line resistance;
c) said computer processor having means for periodically sending coded transmission signals to a first end of said two-wire communications loop, and for receiving said coded transmission signals from the second end of said loop;
d) each of said neuron circuits having means for periodically checking for said coded transmission signals and for actuating said fault switching circuit to one of said plurality of switching states if said coded transmission signals are not received by said neuron circuit, comprising means for switching said fault switching circuit to said first state when said coded transmission signals are detected to be present, and switching said fault switching circuit to said second state when said coded transmission signals are not detected;
and
e) said computer processor having means for periodically checking for the return of said coded transmission signals and for changing the state of its sending coded transmission signals when the return of coded transmission signals is not detected, whereby said computer processor sends coded transmission signals from both of said ends of said communications loop thereafter.

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Dependencies are inferred from the claim text.

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Abstract

a) each node circuit respectively having connections to a neuron circuit associated therewith, and each neuron circuit having means for connection to a data-originating circuit, and means for transferring data from said data-originating circuit to said node circuit;
b) each node circuit respectively having a fault switching circuit interposed between said two-wire communications loop and said neuron circuit, each said fault switching circuit further comprising:
i) a first switching state wherein said communications loop is unbroken and is connected to said neuron circuit associated with said respective node circuit;
ii) a second switching state wherein said communications loop is broken and a first broken end is terminated in a line resistance and a second broken end is connected to said neuron circuit;
iii) a third switching state wherein said communications loop is broken and a first broken end is connected to said neuron circuit and a second broken end is terminated in a line resistance;
and
iv) a fourth switching state wherein said communications loop is broken and both of said broken ends are each terminated in a line resistance;
c) said computer processor having means for periodically sending coded transmission signals to a first end of said two-wire communications loop, and for receiving said coded transmission signals from the second end of said loop;
d) each of said neuron circuits having means for periodically checking for said coded transmission signals and for actuating said fault switching circuit to one of said plurality of switching states if said coded transmission signals are not received by said neuron circuit, comprising means for switching said fault switching circuit to said first state when said coded transmission signals are detected to be present, and switching said fault switching circuit to said second state when said coded transmission signals are not detected;
and
e) said computer processor having means for periodically checking for the return of said coded transmission signals and for changing the state of its sending coded transmission signals when the return of coded transmission signals is not detected, whereby said computer processor sends coded transmission signals from both of said ends of said communications loop thereafter.

8 more elements