US 5,473,652 A · Counter and/or divider arrangement

Abstract

A counter and/or divider arrangement, comprising at least two subsidiary counter circuits, each of which comprises a number of flipflops which are concatenated in respect of their data inputs and outputs, all subsidiary counter circuits receiving a common clock signal, and also comprising at least one logic element, enables the implementation of arbitrary counting operations or division ratios with a low expenditure as regards circuitry and with low-noise operation in that in each logic element signals from the data output of one of the flipflops of at least a part of the subsidiary counter circuits are combined in conformity with an AND-function so as to form an associated resultant signal, each of the resultant signals being applied to at least one of the subsidiary counter circuits as a reset signal in order to switch the subsidiary circuit to an initial state, an output signal being formed from at least one of the resultant signals, the product of the total numbers of flipflops of all subsidiary counter circuits being larger than or equal to a predetermined maximum count or division ratio, the total numbers being determined so that they do not exhibit common prime factors, the data outputs of the flipflops connected to the logic elements of the subsidiary counter circuits being selected so that the output signal exhibits the predetermined maximum count or division ratio.

Claims18

Dependent claims

A counter device for receiving a clock signal and outputting an output count signal at a counter output terminal comprising:

a first subsidiary counter circuit, said first counter circuit having an input for receiving said clock signal, at least one output and a reset terminal and including a plurality of flips-flops arranged in a serial arrangement, each flip-flop having a data input and a data output;
a second subsidiary counter circuit having an input for receiving said clock signal, at least one output and a reset terminal and including a plurality of flip-flops arranged in a serial arrangement;
each flip-flop having a data input and a data output;
and
a logic element having a first input coupled to the data output of one of said flip-flops of said first subsidiary counter circuit, a second input coupled to an output of said second subsidiary counter circuit and an output coupled to said reset terminal of said first subsidiary counter circuit and said counter output terminal of said counter device;
wherein a product of a number of flip-flops of said first subsidiary counter circuit and a number of said flip-flops of said second subsidiary counter circuit is one of greater than and equal to one of a predetermined maximum count and division ratio, said number of flip-flops of said first subsidiary counter circuit and said number of flip-flops not having a common prime factor.

3 more elements

Dependencies are inferred from the claim text.

Counter and/or divider arrangement

Life of this patent

Counter and/or divider arrangement

Life of this patent

Abstract

Claims18