Method and apparatus for testing large embedded counters

A circuit comprising:

• a long counter having N counting stages, each stage having an input and an output, where N is an integer greater than 4;
• means for partitioning said long counter into X sections, each section including a number of said N counting stages interconnected to form a shorter counter than said long counter;
• each section having an input defined by the input of the first counting stage of that section, and each section having an output defined by the output of the last counting stage of that section;
• where X is an integer equal to, or greater than 2;
• said means for partitioning said long counter including a gating means connected between the last stage of a first one of said X sections and the input stage of a second one of said X sections;
• means for applying a control signal to said gating means for normally enabling the gating means to couple the output of said first section to the input of said second section and for, during a test period, decoupling said first and second sections and enabling a predetermined condition to be applied to the inputs of said first and second sections;
• and
• means for, during said test period, selectively and sequentially testing all of said X sections including means for selectively coupling, one at a time, the outputs of each and every stage in a section being tested to a register stage for counting in sequence the outputs of the stages of all the X sections.

A method of testing the operability of an N stage counter, where N is an integer greater than 4 and each stage has an input and an output, comprising the steps of:

• setting the N stages of the counter to a first condition and detecting the presence of the first condition;
• setting the N stages of the counter to a second condition, different than said first condition, and detecting the presence of the second condition;
• partitioning the N stages of the counter into X counter sections, where X is equal to or greater than 2 and less than N;
• and
• during a first time interval:
• (a) applying clocking signals to a first one of said X sections and detecting when said first one of said X sections has counted a predetermined number of clock cycles;
• and (b)
• (b) applying clocking signals to a second one of said X sections and summing the counts produced at the outputs of all the stages of said second section.

The combination comprising,

• a plurality of counter stages, each counter stage having an input and an output;
• X of said counter stages being interconnected to form a first counter section having a first counter input and a first counter output;
• Y of said counter stages being interconnected to form a second counter section having a second counter input and a second counter output;
• where X and Y are integers greater than 2;
• gating means for selectively coupling the first counter output of the first counter section to the second counter input of the second counter section and for, during a testing phase, selectively decoupling the first counter output from the second counter input and for then supplying the same value signal to the first and second counter inputs of the first and second counter sections;
• testing means for, during said testing phase, applying clocking signals to said first and second counter sections, said first section for controlling the number of clocking cycles applied to said second counter section during a first time interval;
• and
• register means coupled to the outputs of all the stages of said second counter section for totalling all the counts of said second section during said first time interval.

A circuit formed on an integrated circuit (IC) comprising:

• a counter having N interconnected counting stages, each counting stage having an input and an output, where N is an integer greater than 4;
• means for testing the operability of the counting stages, including:
• (a) means for partitioning said counter into X sections, each section having N/X stages, where X is an integer equal to, or greater than 2;
• (b) means for applying clocking signals to, at least, first and second ones of said X sections;
• (c) means for detecting when a predetermined number of clock cycles have been applied to a first one of said X sections and thereby defining a first time interval;
• (d) means for, during said first time interval, sensing the outputs of each stage of a second one of said X sections for totalling the outputs produced by said second one of said X sections;
• and
• (e) means for selectively resetting the N counting stages to a certain condition and for detecting the response of the N counting stages to the resetting condition.