Frequency slaving apparatus
AssigneesFrance Telecom, Telediffusion de France
InventorJean-Pierre Bauduin
Life of this patent
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Abstract
A frequency control device comprises, in the form of a phase-locked loop, a phase comparator, a filter, an oscillator producing a local clock signal and two divide-by-M frequency dividers. The dividers receive the local clock signal whose frequency is slaved to N times the frequency of a master clock signal, with M<N, and are looped to the inputs of the comparator. A first of the dividers is reinitialized at the frequency of the master clock signal. A load circuit loads the most-significant-bit stages of a counter included in the first divider with a binary word added to binary elements stored in most-significant-bit stages of a counter included in the second divider, after a resetting of the second divider following a general initialization of the device.
Claims3
Apparatus for slaving the local frequency of a local clock signal to N times the master frequency of a master clock signal, comprising:
- (a) phase comparator means having a first input, a second input, and an output at which a control voltage is produced;
- (b) filter means for filtering said control voltage to produce a filtered control voltage;
- (c) voltage controlled oscillator means having an output at which a local clock signal responsive to said filtered control voltage is produced;
- (d) first frequency divider means and second frequency divider means each including modulo-M counter means having most-significant-bit stages, respectively, where M is a predetermined integer less than N, said first frequency divider means and said second frequency divider means having outputs for supplying first and second slaving control signals to the first input and second input of said phase comparator means, respectively, said first frequency divider means and said second frequency divider means having first inputs connected with the output of said voltage controlled oscillator means, thereby to increment the counters of said first frequency divider means and said second frequency divider means with said local clock signal;
- (e) adder means connected between said most-significant-bit stages of the counters in said first frequency divider means and second frequency divider means for adding a predetermined binary word to binary elements stored in the most-significant-bit stages of the counter of said second frequency divider means, thereby to derive a binary addition result;
- (f) means for supplying a general initializing signal to the counters of said first frequency divider means and said second frequency divider means, thereby to initially load the result of the binary addition into the most-significant-bit stages of the counter of said first frequency divider means;
- and
- (g) means for supplying said master clock signal to said first frequency divider means and said second frequency divider means to periodically reset to zero the counter of said second frequency divider means and to periodically load the most-significant-bit stages of the counter of said first frequency divider means with the binary addition result.
Dependencies are inferred from the claim text.