Clock recovery apparatus with means for sensing an out of lock condition
AssigneeHewlett-Packard Company
InventorsDonald M. Lee, Benny W. H. Lai
Life of this patent
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Abstract
An out of lock condition is sensed on a data transition by transition basis in clock recovery apparatus. When an out of lock condition is sensed, a range sweeping signal is generated and summed with the correction signal to sweep the frequency of the clock signal over the frequency range of the VCO. When an out of lock condition is absent, i.e., when the VCO is phase locked, simulated data transitions are generated in the frequency/phase detector. An out of lock condition is sensed by a D flip-flop. Data is coupled to the clock input of the flip-flop, the clock signal is delayed by a fraction of its nominal period and coupled to the D input of the flip-flop. The state of the Q output of the flip-flop indicates an out of lock condition.
Claims13
Clock recovery apparatus comprising:
- a source of binary data, the binary data having data transitions;
- a voltage controlled oscillator for generating a clock signal that has a variable frequency over a range of frequencies;
- a phase detector responsive to the data transitions and the clock signal for generating a binary error signal having a first value when the actual data transitions lead the clock signal in phase and a second value when the data transitions lag the clock signal in phase;
- first means responsive to changes in the value of the binary error signal for controlling the oscillator to introduce changes in the frequency of the clock signal to phase lock onto the data transitions;
- means for integrating the binary error signal;
- second means responsive to the integrated signal for controlling the oscillator to introduce changes in the frequency of the clock signal to correct the frequency of the oscillator;
- a D flip-flop having a D input, a clock input, and a Q output;
- means for coupling the binary data to the clock input of the flip-flop and coupling the clock signal to the D input of the flip-flop so phased with respect to each other that the Q output of the flip-flop remains unchanged while the clock signal remains phase locked unto the data transitions and the Q output of the flip-flop changes state to designate an out of lock condition while the clock signal is not phase locked unto the data transitions;
- means responsive to the Q output of the flip flop for generating a range sweeping signal;
- and
- means for coupling the range sweeping signal to the oscillator to sweep the frequency of the clock signal over the clock frequency range, thereby reestablishing a phase locked condition.
The apparatus of claim l, additionally comprising means for integrating the Q output of the flip-flop, the range sweep signal being generated after the integrated Q output of the flip-flop reaches a predetermined value.
Clock recovery apparatus comprising:
- a source of binary data on a single data channel, the binary data having data transitions occurring at a given nominal period;
- a voltage controlled oscillator for generating a clock signal that has a variable frequency over a range of frequencies;
- a phase detector responsive to the data transitions on the single data channel and the clock signal for generating a binary error signal having a first value when the data transitions lead the clock signal in phase and a second value when the data transitions lag the clock signal in phase;
- first means responsive to changes in the value of the binary error signal for controlling the oscillator to introduce changes in the frequency of the clock signal to phase lock onto the data transitions;
- means for integrating the binary error signal;
- second means responsive to the integrated signal for controlling the oscillator to introduce changes in the frequency of the clock signal to correct the frequency of the oscillator;
- a D flip-flop having a D input, a clock input, and a Q output having two states;
- and
- means for coupling the binary data to the clock input of the flip-flop and coupling the clock signal to the D input of the flip-flop so phased with respect to each other that the Q output of the flip-flop remains unchanged while the clock signal is phase locked onto the data transitions and the Q output of the flip-flop changes state while the clock signal is not phase locked onto the data transitions.
Dependencies are inferred from the claim text.