US 5,473,638 A · Digital signal processor delay equalization for use in a paging system

Abstract

A method and apparatus provide an equalization time delay to synchronize a plurality of paging transmitters in a simulcast paging system. A delay equalization circuit (41 ) appropriate for use with an analog input signal includes a coder/decoder (CODEC) (50) and a digital signal processor (DSP) (58). An analog input signal is digitized or sampled by an analog-to-digital converter (ADC) in the CODEC, producing corresponding digital values that are input to the DSP. The DSP employs a selected finite impulse filter to interpolate between the sampled digital values from the CODEC to provide enhanced resolution in delaying a signal output that is output. The DSP determines a major sample index and an interpolated filter index to achieve the desired equalization time delay. These variables define two delay intervals that are combined to provide the required equalization time delay. As each sampled digital value is produced, the delayed value is output and converted by a digital-to-analog converter (DAC) 54 in the CODEC to an analog signal having the corresponding required delay. By thus providing the appropriate equalization time delay to the signal transmitted by each paging transmitter in a simulcast paging system 20, differences in the time required for the analog signal to propagate from a paging terminal to each paging transmitter are compensated, thereby substantially eliminating phase interference in overlap zones of the paging transmitters.

Claims29

Dependent claims

A method for compensating differences in propagation times for signals transmitted from a source to a plurality of transmitters in a paging system, so that the plurality of transmitters transmit the signal in synchronization, comprising the steps of:

(a) converting an analog input signal to a digital format by sampling the analog input signal at a first predefined sample rate to produce corresponding sampled digital values, each sampled digital value representing an amplitude of the analog input signal at the time it was sampled;
(b) determining required delay intervals for each transmitter to ensure that the plurality of transmitters are synchronized;
(c) producing at least one digital interpolated value that represents an amplitude of the analog input signal at a time intermediate the times at which the sampled digital values were produced;
(d) storing the sampled digital values and the at least one digital interpolated value;
and
(e) at a second sample rate, selecting an appropriate one of the stored sampled digital values and the at least one digital interpolated value for at least one transmitter to introduce a time delay in the signals transmitted by said at least one of the plurality of transmitters, such that the time delay thus introduced in said signals is substantially equal to a required delay interval for said one of the plurality of transmitters and substantially synchronizes the plurality of transmitters.

3 more elements

A method for providing a required equalization time delay in an output signal transmitted from a site, to compensate for differences in time at which an analog signal is received by the site and by one other site, comprising the steps of:

(a) digitizing the analog signal by sampling it at a fixed rate, producing a plurality of successive sampled digital values, each successive sampled digital value corresponding to a value of the analog signal at successively later points in time;
(b) storing a predefined number of the successive sampled digital values;
(c) interpolating between the successive sampled digital values that were stored to produce a digital interpolated value that corresponds to a value of the analog signal at a point in time occurring between times at which the analog signal is sampled at the fixed rate;
and
(d) transmitting the digital interpolated value that was stored as the output signal, said output signal being delayed by a time interval equal to the equalization time delay so that it is transmitted substantially simultaneously with a corresponding output signal from the other site.

2 more elements

A method for providing a required equalization time delay for an analog signal that is received at one site from another location to compensate for differences in the time required for the analog signal to be received by another site from the other location, comprising the steps of

(a) digitizing the analog signal received from the other location by sampling it at a fixed rate, producing a plurality of sampled digital values, x(n), each sampled digital value corresponding to a value of the analog signal at successively later points in time;
(b) temporarily storing a predefined number, N, of the sampled digital values;
(c) interpolating between a successive pair of sampled digital values that were stored, x(k-1) and x(k), to produce a digital interpolated value, y.sub.m, that corresponds to a value of the analog signal at a point in time occurring between times at which the analog signal is actually sampled at the fixed rate;
and
(d) using the digital interpolated value y.sub.m to produce an output signal that is transmitted, thereby providing the required equalization time delay for the output signal to enable the output signal to be transmitted substantially simultaneously with a corresponding output signal transmitted by said other site.

2 more elements

Apparatus for delaying a signal in order to equalize its propagation time to a transmission site relative to the propagation time for the signal to reach another transmission site, comprising:

(a) means for sampling an input signal at a first sample rate, producing a signal comprising successive sampled digital values, each sampled digital value corresponding to a value of the analog input signal at a later point in time than previously sampled digital values;
(b) memory means, coupled to receive the sampled digital values, for storing said values;
(c) processor means, coupled to selectively recall the sampled digital values stored by the memory means, for digitally filtering the signal from the means for sampling as a function of the sampled digital values stored, producing a digital interpolated value, the digital interpolated value corresponding to an estimated value of the analog input signal at a time intermediate successive pairs of the sampled digital values stored, said processor means determining the digital interpolated value so as to provide a desired time delay before said value is output;
and
(d) means for combining successive digital interpolated values at a predefined rate, to produce a delayed signal to enable each of the transmission sites to substantially simultaneously transmit the signal.

2 more elements

Dependencies are inferred from the claim text.

Digital signal processor delay equalization for use in a paging system

Life of this patent

Digital signal processor delay equalization for use in a paging system

Life of this patent

Abstract

Claims29