High impedance technique for testing interconnections in digital systems
AssigneeHughes Aircraft Company
InventorWilliam D. Farwell
Life of this patent
Estimating the term…
Abstract
A boundary scan transmit cell having a three-state output buffer and logic circuitry for controlling the enabled or disabled state of the three-state buffer as a function of a scan input; and a boundary scan receive cell having an input buffer and a holding circuit for changing the input of the buffer to a predetermined logical state if such input is open or at a high impedance. Also disclosed is a bidirectional boundary scan cell that includes the functions of the disclosed boundary scan transmit and receive scan cells.
Claims3
A boundary scan transmit cell for use in a circuit device having a plurality of device input pins and device output pins wherein each transmit scan cell is associated with a device output pin, the boundary scan transmit cell comprising:
- a scan flip-flop for selectively storing a scan input and for providing a scan flip-flop output that corresponds to the stored scan input;
- a three-state buffer responsive to an input signal for providing a buffered output signal on an associated device output pin;
- a test controller for providing a global disable signal and a test signal;
- selection means responsive to said test controller for providing said test signal or a device signal as said input signal for said three-state buffer;
- disabling means responsive to said scan flip-flop and said test controller for (1) enabling said three-state buffer to provide said buffered output at a first logical state when said global disable signal is of a second logical state and said test signal is of the first logical state, regardless of the state of said scan flip-flop output, (2) disabling said three-state buffer when said global disable signal is of the first logical state regardless of the states of the scan flip-flop output and said test signal, and (3) enabling said three-state buffer to provide said buffered output at the second logical state when said global disable signal is of the second logical state, said scan flip-flop output is of the second logical state, and said test signal is of the second logical state, wherein said disabling means includes:
- (i) an OR gate having a negated input for receiving the scan flip-flop output at its negated input and for receiving the test signal as another input, and
- (ii) an AND gate having a negated input for receiving the global disable signal at its negated input and for receiving the output of said OR gate as another input.
A bidirectional boundary scan cell comprising:
- a transmit scan flip-flop for storing a scan input and providing a scan flip-flop output that corresponds to the stored scan input;
- a three-state buffer responsive to an input signal for providing a buffered output signal on a device input/output pin;
- an input buffer having an input connected to the device input/output pin;
- holding means connected to the input of said input buffer for allowing the input of said input buffer to be driven to a second logical state or a first logical state, and for changing the input to said input buffer to the second logical state if such input is an open connection or a high impedance connection, said holding means allowing the input to the buffer to change to the first logical state when driven to the first logical state;
- a receive scan flip-flop for controllably storing the output of said input buffer;
- a test controller for providing a global disable signal and a test signal;
- selection means responsive to said test controller for providing said test signal or a device signal as said input signal for said three-state buffer;
- and
- disabling means responsive to said scan flip-flop and said test controller for (1) enabling said three-state buffer to provide said buffered output at a first logical state when said global disable signal is of a second logical state and said test signal is of the first logical state, regardless of the state of said scan flip-flop output, (2) disabling said three-state buffer when said global disable signal is of the first logical state regardless of the states of the scan flip-flop output and said test signal, and (3) enabling said three-state buffer when said global disable signal is of the second logical state, said scan flip-flop output is of the first logical state, and said test signal is of the second logical state.
Dependencies are inferred from the claim text.