US 5,473,610 A · Method of clock signal recovery and of synchronization for the reception of information elements transmitted by an ATM network and device for the implementation of the method

Abstract

A clock signal recovery and synchronization method for the reception of information elements transmitted by an ATM network and a device for the implementation of this method. The clock signal recovery is done by the reception of data elements by means of a local clock signal HL with a frequency equal to the frequency of transmission, the rephasing of the data elements being done only after a wait for the presence, on one and the same phase signal, of several fronts or edges of phase signals of the transmitted data that are coherent with a clock pulse HL and by choosing, as a rephasing signal, the phase signal that meets this condition and that frames the clock pulse. The resynchronization is done by the recognition of the resynchronization word with, possibly, a correction of errors in this word. To rephase the transmitted data, a rephasing circuit uses a delay line for generating phase signals and an edge detection circuit for detecting edges of the phase signals that are coherent with the local clock signal. Preferably, the rephasing circuit includes as many flip-flop register stages as there are errors to be corrected in the data. To resynchronize the data for recognizing a delimiter in a precursor of the data, a resynchronization circuit having a series recognition register is used. To correct errors in the delimiter, the resynchronization circuit preferably has stages of registers offset by one bit and connected by logic gates to the series recognition register.

Claims24

Dependent claims

A method of clock signal recovery and synchronization of transmitted data elements at a frequency and in asynchronous temporal transmission mode and occurring in the form of information cells, preceded by a precursor binary data train having edges, said method comprising:

(a) providing a data rephasing and resynchronization circuit for receiving, rephasing, and resynchronizing the transmitted data elements, the data rephasing and resynchronization circuit having a pulsed local clock signal which has a period and frequency, with the frequency of the local clock signal being substantially equal to the transmission frequency of the transmitted data;
(b) receiving at least a precursor binary data train of the transmitted data elements;
(c) generating a number of phase signals from the precursor binary data train with each phase signal delayed from the previous phase signal by a duration equal to the period of the local clock signal divided by the number of phase signals generated;
(d) detecting when one of the phase signals frames at least one pulse of the local clock signal by determining when more than one edge of said phase signal is coherent with a pulse of the local clock signal;
(e) choosing as a data rephasing signal the phase signal framing the local clock signal;
(f) rephasing the transmitted data elements with said data rephasing signal;
and
(g) recognizing a delimiter in the precursor binary data train to resynchronize the reception of information cells in the transmitted data elements.

5 more elements

A device for clock signal recovery and for the synchronization of pulsed data elements transmitted in asynchronous temporal transmission mode and occurring in the form of information cells preceded by a precursor binary data train having edges, a preamble and a delimiter, said device comprising:

a) a rephasing circuit, having (1) a pulsed clock signal with a predetermined period and frequency, for receiving and rephasing the transmitted data elements, said rephasing circuit being capable of rephasing the data elements even in the presence of transmission errors, (2) a delay line for generating a predetermined number of phase delayed signals from the precursor data train with each of said phase delays having a duration of time equal to the period of said pulsed clock signal divided by a desired number of predetermined phase delays, (3) means for detecting edges of the precursor data train that are coherent with at least one pulse of said clock signal, and (4) means for correcting errors that appear in the precursor binary data train;
and
b) a resynchronization circuit having means for recognizing the delimiter in the precursor binary data train and means for correcting errors in the delimiter.

A circuit for rephasing and resynchronizing data elements transmitted at a frequency and having an information cell preceded by a precursor binary data train with edges and a preamble and delimiter each having a number of bits, said circuit comprising:

a rephasing circuit having (1) a pulsed clock signal, (2) a delay line for receiving at least the precursor of the transmitted data elements and for generating phase shifted signals from the received precursor, (3) an edge detecting circuit, in communication with said delay line, for detecting more than one edge of at least one of said phase shifted signals that are coherent with said pulsed clock signal, and (4) a multiplexer in communication with said edge detection circuit, said multiplexer (1) selecting from said phase shifted signals having edges coherent with said pulsed clock signal said phase shifted signal furthest phase shifted from any other said phase shifted signals having coherent edges and (2) providing a data element rephased with said pulsed clock signal;
a resynchronization circuit in communication with said rephasing circuit (1) for receiving said rephased data element, (2) for detecting the delimiter in said rephased data element, and (3) having a plurality of flip-flops with at least one flip-flop for each bit of the delimiter to be detected.

Dependencies are inferred from the claim text.

Method of clock signal recovery and of synchronization for the reception of information elements transmitted by an ATM network and device for the implementation of the method

Life of this patent

Method of clock signal recovery and of synchronization for the reception of information elements transmitted by an ATM network and device for the implementation of the method

Life of this patent

Abstract

Claims24