Signal reproducing apparatus providing PLL circuit controlled by drum motor speed

A signal reproducing apparatus for reading signals containing components of clock signals recorded on a recording medium, comprising:

• motor means for transporting the recording medium;
• signal readout means including a movable element driven by said motor means for reproducing signals recorded on said recording medium,
• velocity detection means connected to said motor means for detecting a relative velocity between said recording medium and said signal readout means and outputting a velocity detection signal corresponding to the detected relative velocity,
• clock signal reproducing means for reproducing said clock signals from the reproduced signals from said signal readout means and outputting a reproduced clock signal, said clock signal reproducing means having a frequency capturing range shifted in accordance with said velocity detection signal,
• a signal demodulating circuit for demodulating said reproduced signals from said signal readout means based on said reproduced clock signals from said clock signal reproducing means,
• buffer memory means receiving demodulated reproduced signals from said signal demodulating circuit for temporarily storing said demodulated reproduced signals, and
• control means connected to said motor means and said velocity detection means for varying the relative velocity between said recording medium and said signal readout means, wherein said control means includes residual buffer target value generating means for storing a target value representing a predetermined portion of the storage capacity of said buffer memory and includes means for deriving a difference value between said target value and a quantity of demodulated reproduced signals stored in the buffer memory means and for controlling the buffer memory means to output the stored demodulated reproduced signals at a constant rate, wherein said difference value is used to control said motor means.