Serial memory
AssigneeHitachi, Ltd.
InventorsJun Miyake, Jun Kitano
Life of this patent
Estimating the term…
Abstract
In a serial memory which internally converts serial input data into parallel data and writes the data into a memory array two or more bits at a time, and which reads data two or more bits at a time from the memory array and internally converts the read data into serial data for output, circuits are provided that allow selective reversing of the order of parallel conversion on the serial input data and of serial conversion on the parallel data read from the memory array. This serial memory is also provided with a memory controller to reverse the ascending or descending order of the access address for the memory array in the read and write operations.
Claims10
A serial memory comprising:
- a serial-parallel converter connected to receive serial input data;
- a memory array into which converted parallel data, received from the serial-parallel converter, is written in a specified number of bits at a time;
- a parallel-serial converter connected to receive data, which was read out a specified number of bits at a time from the memory array, and outputting converted serial data;
- and
- a memory control circuit for generating a sequence of access addresses for the memory array, and for controlling the writing and reading of data to and from locations in the memory array indicated by the access addresses, the memory control circuit including:
- an address generator for controlling the sequence of generation of access addresses by selectively increasing or decreasing the access addresses according to an indication signal and for outputting the access addresses to said memory array in an increasing sequence or a decreasing sequence depending on said indication signal;
- and
- an operation mode controller for outputting said indication signal to said address generator for indicating to the address generator to increase or decrease the sequence of the access addresses to be outputted to said memory array.
A serial memory system comprising:
- a central processing unit;
- and
- a serial memory connected to the central processing unit, the serial memory comprising:
- a serial-parallel converter connected to receive serial input data;
- a memory array into which converted parallel data, received from the serial-parallel converter, is written a specified number of bits at a time;
- a parallel-serial converter connected to receive data, which was read out a specified number of bits at a time from the memory array, and outputting converted serial data;
- and
- a memory control circuit for generating a sequence of access addresses for the memory array according to control signals from the central processing unit to control the writing and reading of data to and from locations in the memory array indicated by the access addresses, the memory control circuit including:
- an address generator for controlling the sequence of generation of access addresses by selectively increasing or decreasing the access addresses according to an indication signal and for outputting the access addresses to said memory array in an increasing sequence or a decreasing sequence depending on said indication signal;
- and
- an operation mode control circuit for outputting said indication signal to said address generator for indicating to the address generator to output an increasing sequence or a decreasing sequence of the access addresses to be outputted to said memory array.
Dependencies are inferred from the claim text.