Multi-port static random access memory with fast write-thru scheme

A multi-port memory, comprising:

• a memory cell having means for storing a logic signal;
• a write port for writing data to said memory cell;
• a read port for reading data from said memory cell;
• a plurality of first address inputs for receiving a first address for selecting said write port;
• a plurality of second address inputs for receiving a second address for selecting said read port;
• first synchronous means for activating said write port in response to said first address upon receipt of a clock signal;
• and
• second asynchronous means for activating said read port in response to said second address without receipt of a clock signal, wherein said read port is activated at substantially the same time as data is written to said memory cell storage means.

A method for writing data through a multi-port memory cell having a latch, write and read address ports coupled to the latch, a clocked write word line coupled to said write address port, a write bit line coupled to said latch and having data thereon, a static read word line coupled to said read address port, and a read bit line coupled to the latch for reading data from said multi-port memory cell, comprising the steps of:

• a) strobing a decoded write address enable signal from said write address port onto said clocked write word line;
• b) writing data from said write bit line into said latch;
• c) producing a decoded read address enable signal from said read address port onto said static read word line;
• wherein said step (c) is not synchronized by a clock, said steps (b) and (c) being carried out substantially simultaneously;
• and
• d) reading data out of the latch onto a read bit line.