Single chip controller-memory device and a memory architecture and methods suitable for implementing the same
AssigneeCirrus Logic, Inc.
InventorG. R. Mohan Rao
Life of this patent
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Abstract
A processing device 107 is provided disposed on a single chip which includes a controller 103 and a memory 104. The controller 103 is coupled to an address bus 202 and a data bus 204. The memory 103 includes a plurality of independently addressable blocks 200 of memory cells, each block 200 coupled to the address bus 202 and having a selected number of output lines coupled to the data bus 204. The controller 103 accesses a location of the selected number of memory cells of a selected one of the blocks 200 through an address presented on the address bus 202.
Claims38
A processing device disposed on a single chip comprising:
- a controller coupled to an address bus and a data bus;
- and
- a memory comprising:
- a plurality of independently addressable blocks of memory cells, each said block coupled to said address bus and having a selected number of output lines coupled to said data bus, said controller accessing a location comprising a selected number of said memory cells of each of a selected number of said blocks as required to support controller operation via said data bus with a single address word including both row and column address bits simultaneously presented on said address bus.
A memory architecture comprising:
- a plurality of blocks of memory cells, each said block having a plurality of storage locations each for storing n-bit words of data and n number of data lines;
- and
- a plurality of address decoders, each said address decoder coupled to a corresponding one of said blocks, said address decoders allowing access by an associated processor through said data lines of a selected said location in a selected number of said blocks simultaneously in response to simultaneously received row and column address bits,
An integrated circuit comprising:
- a controller;
- an j-bit wide address bus coupled to an address port of said controller;
- an m-bit wide data bus coupled to a data port of said controller;
- and
- a memory comprising:
- z number blocks of memory cells, said cells of each said block organized as an array x number of rows and y number of columns, each said block having n number of data lines coupled to said data bus;
- and
- z number of address decoders coupled to said address bus, each of said decoders coupled to a corresponding said block, an address provided to said decoders allowing access to an n-bit storage location of a selected number of said blocks as required to support operation of said controller via said m-bit wide data bus.
A processing system:
- a central processing unit;
- a system bus coupled to said processing unit;
- display generation apparatus;
- display control circuitry disposed on a single chip and coupled to said system bus and said display apparatus comprising:
- a display controller;
- an j-bit wide address bus coupled to an address pore of said controller;
- an m-bit wide data bus coupled to a data port of said controller;
- and
- a frame buffer memory comprising:
- z number blocks of memory cells, said cells of each said block organized as an array x number of rows and y number of columns, each said block having n number of data lines coupled to said data bus;
- and
- z number of address decoders coupled to said address bus, each of said decoders coupled to a corresponding said block, an address provided to said decoders allowing access to an n-bit storage location of a selected number of said blocks via said m-bit data bus, wherein said selected number of said blocks is determined as required to support operation of said controller.
A method of utilizing memory space in a memory array comprising the steps of:
- partitioning the array into a plurality of blocks of memory cells;
- providing each block with n number of data lines for exchanging data with n-bit locations within such block;
- assigning a different range of memory addresses to each block of memory, each address simultaneously including row and column address bits;
- and
- accessing simultaneously n-bit words from the n-bit locations of a selected number of operational ones of the blocks as required in a selected processing application by presenting an address to the decoders assigned to the operational blocks of memory.
Dependencies are inferred from the claim text.