US 5,473,571 AGranted

Data hold circuit

AssigneeNippon Telegraph and Telephone Corporation

InventorsSatoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya

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Abstract

A data hold circuit storing a logic state of a predetermined node of a logic circuit immediately before power supply to the logic circuit is interrupted, and restoring the stored logic state to the predetermined node immediately after the power supply is restarted. The data hold circuit includes a memory circuit storing the logic state of the node, a switch circuit connected between the memory circuit and the node, and a control circuit controlling the on/off operation of the switch circuit. The control circuit turns on the switch circuit for a predetermined time period when the power supply is changed from on to off, or from off to on. The memory circuit is continuously supplied with power from a power supply other than that for the logic circuit. While the power supply to the logic circuit is in a steady state either in the power on state or power off state, the switch circuit is kept off, thereby preventing effect of the memory circuit on the logic circuit.

Claims20

Dependent claims

A data hold circuit connected to a logic circuit which has a normal mode and a power-saving mode as operation modes, said logic circuit operating normally in the normal mode, and performing power saving in the power-saving mode by interrupting power to the logic circuit or by reducing a clock frequency of the logic circuit, said data hold circuit comprising:

a memory circuit which is continuously supplied with power, at least 1-bit data being writable into and readable from said memory circuit;
a switch circuit including at least one switch element connected between a predetermined node in said logic circuit and said memory circuit;
and
a control circuit controlling said switch circuit, said control circuit holding said switch element in an off state in said normal mode, holding said switch element in an ON state at least for a first predetermined time period at a transition from said normal mode to said power-saving mode, and holding said switch element in an ON state at least for a second predetermined time period at a transition from said power-saving mode to said normal mode.

1 more element

Dependencies are inferred from the claim text.